| 2006 |
|---|
| 11 | EE | Jiann-Chyi Rau,
Chien-Shiun Chen,
Po-Han Wu:
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs.
APCCAS 2006: 1399-1402 |
| 10 | EE | Jiann-Chyi Rau,
Po-Han Wu,
Chia-Jung Liu:
A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits.
APCCAS 2006: 1883-1886 |
| 9 | EE | Jiann-Chyi Rau,
Jun-Yi Chang,
Chien-Shiun Chen:
A broadcast-based test scheme for reducing test size and application time.
ISCAS 2006 |
| 2005 |
|---|
| 8 | EE | Jiann-Chyi Rau,
Ying-Fu Ho,
Po-Han Wu:
A novel reseeding mechanism for pseudo-random testing of VLSI circuits.
ISCAS (3) 2005: 2979-2982 |
| 7 | EE | Jiann-Chyi Rau,
Chih-Lung Chien,
Jia-Shing Ma:
Reconfigurable multiple scan-chains for reducing test application time of SOCs.
ISCAS (6) 2005: 5846-5849 |
| 2004 |
|---|
| 6 | EE | Jiann-Chyi Rau,
Ching-Hsiu Lin,
Jun-Yi Chang:
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains.
Asian Test Symposium 2004: 82-87 |
| 2003 |
|---|
| 5 | EE | Jiann-Chyi Rau,
Yi-Yuan Chang,
Chia-Hung Lin:
An Efficient Mechanism for Debugging RTL Description.
IWSOC 2003: 370-373 |
| 4 | EE | Jiann-Chyi Rau,
Kuo-Chun Kuo:
An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI Circuits.
IWSOC 2003: 374-377 |
| 2002 |
|---|
| 3 | EE | Jiann-Chyi Rau,
Y. M. Chen,
Shih-Chieh Chang:
A don't-care based image circuit for function verification.
ISCAS (5) 2002: 325-328 |
| 2001 |
|---|
| 2 | EE | Shih-Chieh Chang,
Jiann-Chyi Rau:
A timing-driven pseudoexhaustive testing for VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 147-158 (2001) |
| 1998 |
|---|
| 1 | EE | Wen-Ben Jone,
Jiann-Chyi Rau,
Shih-Chieh Chang,
Yu-Liang Wu:
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.
ITC 1998: 322-330 |
