| |
| 1995 | ||
|---|---|---|
| 3 | Shuji Kikuchi, Yoshihiko Hayashi, Takashi Suga, Jun Saitou, Masahiko Kaneko, Takashi Matsumoto, Ryozou Yoshino: A Gate-Array-Based 666MHz VLSI Test System. ITC 1995: 451-458 | |
| 1989 | ||
| 2 | Shuji Kikuchi, Yoshihiko Hayashi, Takashi Matsumoto, Ryozou Yoshino, Ryuichi Takagi: A 250 MHz Shared-Resource VLSI Test System with High Pin Count and Memory Test Capability. ITC 1989: 558-566 | |
| 1985 | ||
| 1 | Ryozou Yoshino, Ryuichi Takagi: Custom VLSI Test System. ITC 1985: 431-437 | |
| 1 | Yoshihiko Hayashi | [2] [3] |
| 2 | Masahiko Kaneko | [3] |
| 3 | Shuji Kikuchi | [2] [3] |
| 4 | Takashi Matsumoto | [2] [3] |
| 5 | Jun Saitou | [3] |
| 6 | Takashi Suga | [3] |
| 7 | Ryuichi Takagi | [1] [2] |