| 2007 |
|---|
| 10 | | Maria Gkatziani,
Rohit Kapur,
Qing Su,
Ben Mathew,
Roberto Mattiuzzo,
Laura Tarantini,
Cy Hay,
Salvatore Talluto,
Thomas W. Williams:
Accurately Determining Bridging Defects from Layout.
DDECS 2007: 87-90 |
| 2005 |
|---|
| 9 | EE | Peter Wohl,
John A. Waicukauski,
Sanjay Patel,
Cy Hay,
Emil Gizdarski,
Ben Mathew:
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST.
VTS 2005: 359-365 |
| 2004 |
|---|
| 8 | EE | Davide Appello,
Alessandra Fudoli,
Katia Giarda,
Emil Gizdarski,
Ben Mathew,
Vincenzo Tancorre:
Yield Analysis of Logic Circuits.
VTS 2004: 103-108 |
| 7 | EE | Davide Appello,
Alessandra Fudoli,
Katia Giarda,
Vincenzo Tancorre,
Emil Gizdarski,
Ben Mathew:
Understanding Yield Losses in Logic Circuits.
IEEE Design & Test of Computers 21(3): 208-215 (2004) |
| 1999 |
|---|
| 6 | EE | Ben Mathew,
Daniel G. Saab:
Combining multiple DFT schemes with test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 685-696 (1999) |
| 1998 |
|---|
| 5 | EE | Young-Jun Kwon,
Ben Mathew,
Hong Hao:
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays.
ITC 1998: 727- |
| 1997 |
|---|
| 4 | EE | Junji Mori,
Ben Mathew,
Dave Burns,
Yeuk-Hai Mok:
Testability Features of R10000 Microprocessor.
Asian Test Symposium 1997: 108-111 |
| 1995 |
|---|
| 3 | | Ben Mathew,
Daniel G. Saab:
DFT & ATPG: Together Again.
ITC 1995: 262-271 |
| 1993 |
|---|
| 2 | EE | Ben Mathew,
Daniel G. Saab:
Augmented partial reset.
ICCAD 1993: 716-719 |
| 1 | | Miron Abramovici,
Prashant S. Parikh,
Ben Mathew,
Daniel G. Saab:
On Selecting Flip-Flops for Partial Reset.
ITC 1993: 1008-1012 |
