| 2008 |
|---|
| 26 | EE | Yong-Je Goo,
Hanho Lee:
Two bit-level pipelined viterbi decoder for high-performance UWB applications.
ISCAS 2008: 1012-1015 |
| 25 | EE | Sangmin Kim,
Gerald E. Sobelman,
Hanho Lee:
Adaptive quantization in min-sum based irregular LDPC decoder.
ISCAS 2008: 536-539 |
| 24 | EE | Minhyeok Shin,
Hanho Lee:
A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications.
ISCAS 2008: 960-963 |
| 23 | EE | Sangho Yoon,
Hanho Lee:
A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders.
SoCC 2008: 379-382 |
| 22 | EE | Seungbeom Lee,
Hanho Lee:
A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders.
IEICE Transactions 91-A(3): 830-835 (2008) |
| 21 | EE | Jeesung Lee,
Hanho Lee:
A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems.
IEICE Transactions 91-A(4): 1206-1211 (2008) |
| 2007 |
|---|
| 20 | EE | Yong-Min Lee,
Chang-Seok Choi,
Seung-Gon Hwang,
Hyun Dong Kim,
Chul Hong Min,
Jae-Hyun Park,
Hanho Lee,
Tae-Seon Kim,
Chong Ho Lee:
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications.
ARC 2007: 283-292 |
| 19 | EE | Seungbeom Lee,
Hanho Lee,
Jongyoon Shin,
Je-Soo Ko:
A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders.
ISCAS 2007: 901-904 |
| 18 | EE | Cheol-Ho Shin,
Sangsung Choi,
Hanho Lee,
Jeong-Ki Pack:
A Design and Performance of 4-Parallel MB-OFDM UWB Receiver.
IEICE Transactions 90-B(3): 672-675 (2007) |
| 17 | EE | Chang-Seok Choi,
Hanho Lee:
A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform.
IEICE Transactions 90-D(12): 1932-1938 (2007) |
| 2006 |
|---|
| 16 | EE | Yeong-Jae Oh,
Hanho Lee,
Chong Ho Lee:
Dynamic Partial Reconfigurable FIR Filter Design.
ARC 2006: 30-35 |
| 15 | EE | Jeesung Lee,
Hanho Lee,
Sang-in Cho,
Sangsung Choi:
A high-speed, low-complexity radix-24 FFT processor for MB-OFDM UWB systems.
ISCAS 2006 |
| 14 | EE | Yeong-Jae Oh,
Hanho Lee,
Chong Ho Lee:
A reconfigurable FIR filter design using dynamic partial reconfiguration.
ISCAS 2006 |
| 13 | EE | Hanho Lee,
Chang-Seok Choi:
Implementation of a FIR Filter on a Partial Reconfigurable Platform.
KES (3) 2006: 108-115 |
| 2005 |
|---|
| 12 | EE | Hanho Lee:
An ultra high-speed Reed-Solomon decoder.
ISCAS (2) 2005: 1036-1039 |
| 11 | EE | Hanho Lee:
Reconfigurable Power-Aware Scalable Booth Multiplier.
KES (1) 2005: 176-183 |
| 10 | EE | In Ja Jeon,
Phill-Kyu Rhee,
Hanho Lee:
An Evolvable Hardware System Under Uneven Environment.
KES (2) 2005: 319-326 |
| 9 | EE | Hanho Lee:
Power-Aware Scalable Pipelined Booth Multiplier.
IEICE Transactions 88-A(11): 3230-3234 (2005) |
| 2004 |
|---|
| 8 | EE | Hanho Lee,
Gerald E. Sobelman:
VLSI Design Of Digit-Serial FPGA Architecture.
Journal of Circuits, Systems, and Computers 13(1): 17-52 (2004) |
| 2003 |
|---|
| 7 | EE | Hanho Lee:
High-speed VLSI architecture for parallel Reed-Solomon decoder.
ISCAS (2) 2003: 320-323 |
| 6 | EE | Hanho Lee:
An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder.
ISVLSI 2003: 209-210 |
| 5 | EE | Hanho Lee:
High-speed VLSI architecture for parallel Reed-Solomon decoder.
IEEE Trans. VLSI Syst. 11(2): 288-294 (2003) |
| 1999 |
|---|
| 4 | EE | Lijun Gao,
Sarvesh Shrivastava,
Hanho Lee,
Gerald E. Sobelman:
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor.
FCCM 1999: 304-305 |
| 1998 |
|---|
| 3 | EE | Hanho Lee,
Gerald E. Sobelman:
Digit-Serial DSP Library for Optimized FPGA Configuration.
FCCM 1998: 322-323 |
| 2 | EE | Hanho Lee,
Sarvesh Shrivastava,
Gerald E. Sobelman:
FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract).
FPGA 1998: 257 |
| 1997 |
|---|
| 1 | EE | Hanho Lee,
Gerald E. Sobelman:
A New Low-Voltage Full Adder Circuit.
Great Lakes Symposium on VLSI 1997: 88- |
