| |
| 2004 | ||
|---|---|---|
| 3 | EE | Yao-Wen Chang, Shih-Ping Lin: MR: a new framework for multilevel full-chip routing. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 793-800 (2004) |
| 2003 | ||
| 2 | EE | Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin: Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. IEEE Trans. VLSI Syst. 11(4): 679-686 (2003) |
| 2002 | ||
| 1 | EE | Shih-Ping Lin, Yao-Wen Chang: A novel framework for multilevel routing considering routability and performance. ICCAD 2002: 44-50 |
| 1 | Yao-Wen Chang | [1] [2] [3] |
| 2 | Jai-Ming Lin | [2] |