D. Harris

List of publications from the DBLP Bibliography Server - FAQ

2003

3 EE D. Harris, S. Naffziger: Correction to "statistical clock skew modeling with data delay variations". IEEE Trans. VLSI Syst. 11(2): 295-296 (2003)

2001

2 EE D. Harris, S. Naffziger: Statistical clock skew modeling with data delay variations. IEEE Trans. VLSI Syst. 9(6): 888-898 (2001)

1995

1 Tamás D. Gedeon, Patrick M. Wong, D. Harris: Balancing Bias and Variance: Network Topology and Pattern Set Reduction Techniques. IWANN 1995: 551-558

2003
3	EE	D. Harris, S. Naffziger: Correction to "statistical clock skew modeling with data delay variations". IEEE Trans. VLSI Syst. 11(2): 295-296 (2003)
2001
2	EE	D. Harris, S. Naffziger: Statistical clock skew modeling with data delay variations. IEEE Trans. VLSI Syst. 9(6): 888-898 (2001)
1995
1		Tamás D. Gedeon, Patrick M. Wong, D. Harris: Balancing Bias and Variance: Network Topology and Pattern Set Reduction Techniques. IWANN 1995: 551-558

Coauthor Index