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M. S. Hrishikesh

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2003
4EEHeather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger: Static energy reduction techniques for microprocessor caches. IEEE Trans. VLSI Syst. 11(3): 303-313 (2003)
2002
3EEM. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas: The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. ISCA 2002: 14-24
2001
2 Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger: Static Energy Reduction Techniques for Microprocessor Caches. ICCD 2001: 276-283
2000
1EEVikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger: Clock rate versus IPC: the end of the road for conventional microarchitectures. ISCA 2000: 248-259

Coauthor Index

1Vikas Agarwal [1] [2] [4]
2Doug Burger [1] [2] [3] [4]
3Keith I. Farkas [3]
4Heather Hanson [2] [4]
5Norman P. Jouppi [3]
6Stephen W. Keckler [1] [2] [3] [4]
7Premkishore Shivakumar [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)