| 2003 |
|---|
| 4 | EE | Heather Hanson,
M. S. Hrishikesh,
Vikas Agarwal,
Stephen W. Keckler,
Doug Burger:
Static energy reduction techniques for microprocessor caches.
IEEE Trans. VLSI Syst. 11(3): 303-313 (2003) |
| 2002 |
|---|
| 3 | EE | M. S. Hrishikesh,
Doug Burger,
Stephen W. Keckler,
Premkishore Shivakumar,
Norman P. Jouppi,
Keith I. Farkas:
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.
ISCA 2002: 14-24 |
| 2001 |
|---|
| 2 | | Heather Hanson,
M. S. Hrishikesh,
Vikas Agarwal,
Stephen W. Keckler,
Doug Burger:
Static Energy Reduction Techniques for Microprocessor Caches.
ICCD 2001: 276-283 |
| 2000 |
|---|
| 1 | EE | Vikas Agarwal,
M. S. Hrishikesh,
Stephen W. Keckler,
Doug Burger:
Clock rate versus IPC: the end of the road for conventional microarchitectures.
ISCA 2000: 248-259 |
