| 2007 |
|---|
| 12 | EE | Georges G. E. Gielen,
Wim Dehaene,
Phillip Christie,
Dieter Draxelmayr,
Edmond Janssens,
Karen Maex,
Ted Vucurevich:
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
CoRR abs/0710.4709: (2007) |
| 2005 |
|---|
| 11 | EE | Georges G. E. Gielen,
Wim Dehaene,
Phillip Christie,
Dieter Draxelmayr,
Edmond Janssens,
Karen Maex,
Ted Vucurevich:
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
DATE 2005: 36-42 |
| 10 | EE | Viet H. Nguyen,
Phillip Christie:
The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits.
SLIP 2005: 73-78 |
| 2003 |
|---|
| 9 | EE | Phillip Christie:
Guest editorial: System-level interconnect prediction.
IEEE Trans. VLSI Syst. 11(1): 1-2 (2003) |
| 8 | EE | Raymond A. Wildman,
Joshua I. Kramer,
Daniel S. Weile,
Phillip Christie:
Multi-objective optimization of interconnect geometry.
IEEE Trans. VLSI Syst. 11(1): 15-23 (2003) |
| 7 | EE | Phillip Christie,
José Pineda de Gyvez:
Prelayout interconnect yield prediction.
IEEE Trans. VLSI Syst. 11(1): 55-59 (2003) |
| 2002 |
|---|
| 6 | EE | Stephen E. Krufka,
Phillip Christie:
Terminal optimization analysis for functional block re-use.
SLIP 2002: 3-8 |
| 5 | EE | Muzammil Iqbal,
Ahmed Sharkawy,
Usman Hameed,
Phillip Christie:
Stochastic wire length sampling for cycle time estimation.
SLIP 2002: 91-96 |
| 4 | EE | Raymond A. Wildman,
Joshua I. Kramer,
Daniel S. Weile,
Phillip Christie:
Wire layer geometry optimization using stochastic wire sampling.
SLIP 2002: 97-102 |
| 2001 |
|---|
| 3 | EE | Phillip Christie,
José Pineda de Gyvez:
Pre-layout prediction of interconnect manufacturability.
SLIP 2001: 167-173 |
| 2000 |
|---|
| 2 | EE | Phillip Christie:
Managing interconnect resources (tutorial).
SLIP 2000: 1-51 |
| 1995 |
|---|
| 1 | | Phillip Christie,
Mark D. Loose,
Alexander V. Chernoguzov:
Simulated Isobaric Annealing.
ISCAS 1995: 1683-1686 |
