2009 |
54 | EE | Mark Gebhart,
Bertrand A. Maher,
Katherine E. Coons,
Jeff Diamond,
Paul Gratz,
Mario Marino,
Nitya Ranganathan,
Behnam Robatmili,
Aaron Smith,
James H. Burrill,
Stephen W. Keckler,
Doug Burger,
Kathryn S. McKinley:
An evaluation of the TRIPS computer system.
ASPLOS 2009: 1-12 |
53 | EE | Boris Grot,
Joel Hestness,
Stephen W. Keckler,
Onur Mutlu:
Express Cube Topologies for on-Chip Interconnects.
HPCA 2009: 163-174 |
2008 |
52 | EE | Paul Gratz,
Boris Grot,
Stephen W. Keckler:
Regional congestion awareness for load balance in networks-on-chip.
HPCA 2008: 203-214 |
51 | EE | Franziska Roesner,
Doug Burger,
Stephen W. Keckler:
Counting Dependence Predictors.
ISCA 2008: 215-226 |
50 | EE | Divya Gulati,
Changkyu Kim,
Simha Sethumadhavan,
Stephen W. Keckler,
Doug Burger:
Multitasking workload scheduling on flexible-core chip multiprocessors.
PACT 2008: 187-196 |
49 | EE | Jeffrey R. Diamond,
Behnam Robatmili,
Stephen W. Keckler,
Robert A. van de Geijn,
Kazushige Goto,
Doug Burger:
High performance dense linear algebra on a spatially distributed processor.
PPOPP 2008: 63-72 |
2007 |
48 | EE | Michael T. Clark,
Peter Hofstee,
Edward J. Barragy,
Ian Buck,
Stephen W. Keckler:
The future of multi-core technologies.
CLUSTER 2007 |
47 | EE | Heather Hanson,
Stephen W. Keckler,
Karthick Rajamani,
Soraya Ghiasi,
Freeman L. Rawson III,
Juan Rubio:
Power, Performance, and Thermal Management for High-Performance Systems.
IPDPS 2007: 1-8 |
46 | EE | Simha Sethumadhavan,
Franziska Roesner,
Joel S. Emer,
Doug Burger,
Stephen W. Keckler:
Late-binding: enabling unordered load-store queues.
ISCA 2007: 347-357 |
45 | EE | Heather Hanson,
Stephen W. Keckler,
Soraya Ghiasi,
Karthick Rajamani,
Freeman L. Rawson III,
Juan Rubio:
Thermal response to DVFS: analysis with an Intel Pentium M.
ISLPED 2007: 219-224 |
44 | EE | Changkyu Kim,
Simha Sethumadhavan,
M. S. Govindan,
Nitya Ranganathan,
Divya Gulati,
Doug Burger,
Stephen W. Keckler:
Composable Lightweight Processors.
MICRO 2007: 381-394 |
43 | EE | Paul Gratz,
Karthikeyan Sankaralingam,
Heather Hanson,
Premkishore Shivakumar,
Robert G. McDonald,
Stephen W. Keckler,
Doug Burger:
Implementation and Evaluation of a Dynamically Routed Processor Operand Network.
NOCS 2007: 7-17 |
42 | EE | Jayaram Mudigonda,
Harrick M. Vin,
Stephen W. Keckler:
Reconciling performance and programmability in networking systems.
SIGCOMM 2007: 73-84 |
41 | EE | Paul Gratz,
Changkyu Kim,
Karthikeyan Sankaralingam,
Heather Hanson,
Premkishore Shivakumar,
Stephen W. Keckler,
Doug Burger:
On-Chip Interconnection Networks of the TRIPS Chip.
IEEE Micro 27(5): 41-50 (2007) |
40 | EE | John D. Owens,
William J. Dally,
Ron Ho,
D. N. Jayasimha,
Stephen W. Keckler,
Li-Shiuan Peh:
Research Challenges for On-Chip Interconnection Networks.
IEEE Micro 27(5): 96-108 (2007) |
39 | EE | Jaehyuk Huh,
Changkyu Kim,
Hazim Shafi,
Lixin Zhang,
Doug Burger,
Stephen W. Keckler:
A NUCA Substrate for Flexible CMP Cache Sharing.
IEEE Trans. Parallel Distrib. Syst. 18(8): 1028-1040 (2007) |
2006 |
38 | EE | Simha Sethumadhavan,
Robert G. McDonald,
Rajagopalan Desikan,
Doug Burger,
Stephen W. Keckler:
Design and Implementation of the TRIPS Primary Memory System.
ICCD 2006 |
37 | EE | Paul Gratz,
Changkyu Kim,
Robert G. McDonald,
Stephen W. Keckler,
Doug Burger:
Implementation and Evaluation of On-Chip Network Architectures.
ICCD 2006 |
36 | EE | Kartik K. Agaram,
Stephen W. Keckler,
Calvin Lin,
Kathryn S. McKinley:
Decomposing memory performance: data structures and phases.
ISMM 2006: 95-103 |
35 | EE | Ramadass Nagarajan,
Xia Chen,
Robert G. McDonald,
Doug Burger,
Stephen W. Keckler:
Critical path analysis of the TRIPS architecture.
ISPASS 2006: 37-47 |
34 | EE | Karthikeyan Sankaralingam,
Ramadass Nagarajan,
Robert G. McDonald,
Rajagopalan Desikan,
Saurabh Drolia,
M. S. Govindan,
Paul Gratz,
Divya Gulati,
Heather Hanson,
Changkyu Kim,
Haiming Liu,
Nitya Ranganathan,
Simha Sethumadhavan,
Sadia Sharif,
Premkishore Shivakumar,
Stephen W. Keckler,
Doug Burger:
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.
MICRO 2006: 480-491 |
33 | EE | Aaron Smith,
Ramadass Nagarajan,
Karthikeyan Sankaralingam,
Robert G. McDonald,
Doug Burger,
Stephen W. Keckler,
Kathryn S. McKinley:
Dataflow Predication.
MICRO 2006: 89-102 |
2005 |
32 | EE | Jaehyuk Huh,
Changkyu Kim,
Hazim Shafi,
Lixin Zhang,
Doug Burger,
Stephen W. Keckler:
A NUCA substrate for flexible CMP cache sharing.
ICS 2005: 31-40 |
2004 |
31 | EE | Rajagopalan Desikan,
Simha Sethumadhavan,
Doug Burger,
Stephen W. Keckler:
Scalable selective re-execution for EDGE architectures.
ASPLOS 2004: 120-132 |
30 | EE | Ramadass Nagarajan,
Sundeep K. Kushwaha,
Doug Burger,
Kathryn S. McKinley,
Calvin Lin,
Stephen W. Keckler:
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures.
IEEE PACT 2004: 74-84 |
29 | EE | Doug Burger,
Stephen W. Keckler,
Kathryn S. McKinley,
Michael Dahlin,
Lizy Kurian John,
Calvin Lin,
Charles R. Moore,
James H. Burrill,
Robert G. McDonald,
William Yode:
Scaling to the End of Silicon with EDGE Architectures.
IEEE Computer 37(7): 44-55 (2004) |
28 | EE | Simha Sethumadhavan,
Rajagopalan Desikan,
Doug Burger,
Charles R. Moore,
Stephen W. Keckler:
Scalable Hardware Memory Disambiguation for High-ILP Processors.
IEEE Micro 24(6): 118-127 (2004) |
27 | EE | Doug Burger,
Todd M. Austin,
Stephen W. Keckler:
Recent extensions to the SimpleScalar tool suite.
SIGMETRICS Performance Evaluation Review 31(4): 4-7 (2004) |
26 | EE | Karthikeyan Sankaralingam,
Ramadass Nagarajan,
Haiming Liu,
Changkyu Kim,
Jaehyuk Huh,
Nitya Ranganathan,
Doug Burger,
Stephen W. Keckler,
Robert G. McDonald,
Charles R. Moore:
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP.
TACO 1(1): 62-93 (2004) |
2003 |
25 | EE | Karthikeyan Sankaralingam,
Vincent Ajay Singh,
Stephen W. Keckler,
Doug Burger:
Routed Inter-ALU Networks for ILP Scalability and Performance.
ICCD 2003: 170- |
24 | EE | Premkishore Shivakumar,
Stephen W. Keckler,
Charles R. Moore,
Doug Burger:
Exploiting Microarchitectural Redundancy For Defect Tolerance.
ICCD 2003: 481-488 |
23 | EE | Karthikeyan Sankaralingam,
Ramadass Nagarajan,
Haiming Liu,
Changkyu Kim,
Jaehyuk Huh,
Doug Burger,
Stephen W. Keckler,
Charles R. Moore:
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture.
ISCA 2003: 422-433 |
22 | EE | Karthik Natarajan,
Heather Hanson,
Stephen W. Keckler,
Charles R. Moore,
Doug Burger:
Microprocessor pipeline energy analysis.
ISLPED 2003: 282-287 |
21 | EE | Karthikeyan Sankaralingam,
Stephen W. Keckler,
William R. Mark,
Doug Burger:
Universal Mechanisms for Data-Parallel Architectures.
MICRO 2003: 303-314 |
20 | EE | Simha Sethumadhavan,
Rajagopalan Desikan,
Doug Burger,
Charles R. Moore,
Stephen W. Keckler:
Scalable Hardware Memory Disambiguation for High ILP Processors.
MICRO 2003: 399-410 |
19 | EE | Karthikeyan Sankaralingam,
Ramadass Nagarajan,
Haiming Liu,
Changkyu Kim,
Jaehyuk Huh,
Doug Burger,
Stephen W. Keckler,
Charles R. Moore:
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture.
IEEE Micro 23(6): 46-51 (2003) |
18 | EE | Changkyu Kim,
Doug Burger,
Stephen W. Keckler:
Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches.
IEEE Micro 23(6): 99-107 (2003) |
17 | EE | Heather Hanson,
M. S. Hrishikesh,
Vikas Agarwal,
Stephen W. Keckler,
Doug Burger:
Static energy reduction techniques for microprocessor caches.
IEEE Trans. VLSI Syst. 11(3): 303-313 (2003) |
2002 |
16 | EE | Changkyu Kim,
Doug Burger,
Stephen W. Keckler:
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches.
ASPLOS 2002: 211-222 |
15 | EE | Premkishore Shivakumar,
Michael Kistler,
Stephen W. Keckler,
Doug Burger,
Lorenzo Alvisi:
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic.
DSN 2002: 389-398 |
14 | EE | M. S. Hrishikesh,
Doug Burger,
Stephen W. Keckler,
Premkishore Shivakumar,
Norman P. Jouppi,
Keith I. Farkas:
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.
ISCA 2002: 14-24 |
13 | EE | Rajagopalan Desikan,
Doug Burger,
Stephen W. Keckler,
Llorenc Cruz,
Fernando Latorre,
Antonio González,
Mateo Valero:
Errata on "Measuring Experimental Error in Microprocessor Simulation".
SIGARCH Computer Architecture News 30(1): 2-4 (2002) |
2001 |
12 | | Heather Hanson,
M. S. Hrishikesh,
Vikas Agarwal,
Stephen W. Keckler,
Doug Burger:
Static Energy Reduction Techniques for Microprocessor Caches.
ICCD 2001: 276-283 |
11 | EE | Jaehyuk Huh,
Doug Burger,
Stephen W. Keckler:
Exploring the Design Space of Future CMPs.
IEEE PACT 2001: 199-210 |
10 | EE | Ramadass Nagarajan,
Karthikeyan Sankaralingam,
Doug Burger,
Stephen W. Keckler:
A design space evaluation of grid processor architectures.
MICRO 2001: 40-51 |
2000 |
9 | EE | Vikas Agarwal,
M. S. Hrishikesh,
Stephen W. Keckler,
Doug Burger:
Clock rate versus IPC: the end of the road for conventional microarchitectures.
ISCA 2000: 248-259 |
8 | EE | Nicholas P. Carter,
William J. Dally,
Whay Sing Lee,
Stephen W. Keckler,
Andrew Chang:
Processor Mechanisms for Software Shared Memory.
ISHPC 2000: 120-133 |
7 | EE | Daniel A. Jiménez,
Stephen W. Keckler,
Calvin Lin:
The impact of delay on the design of branch predictors.
MICRO 2000: 67-76 |
1999 |
6 | | Stephen W. Keckler,
Andrew Chang,
Whay Sing Lee,
Sandeep Chatterjee,
William J. Dally:
Concurrent Event Handling through Multithreading.
IEEE Trans. Computers 48(9): 903-916 (1999) |
1998 |
5 | EE | Stephen W. Keckler,
William J. Dally,
Daniel Maskit,
Nicholas P. Carter,
Andrew Chang,
Whay Sing Lee:
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor.
ISCA 1998: 306-317 |
4 | | Whay Sing Lee,
William J. Dally,
Stephen W. Keckler,
Nicholas P. Carter,
Andrew Chang:
An Efficient, Protected Message Interface.
IEEE Computer 31(11): 69-75 (1998) |
1995 |
3 | EE | Marco Fillo,
Stephen W. Keckler,
William J. Dally,
Nicholas P. Carter,
Andrew Chang,
Yevgeny Gurevich,
Whay Sing Lee:
The M-Machine multicomputer.
MICRO 1995: 146-156 |
1994 |
2 | | Nicholas P. Carter,
Stephen W. Keckler,
William J. Dally:
Hardware Support for Fast Capability-based Addressing.
ASPLOS 1994: 319-327 |
1992 |
1 | | Stephen W. Keckler,
William J. Dally:
Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism.
ISCA 1992: 202-213 |