| 2005 |
|---|
| 7 | EE | Yu Cao,
Xuejue Huang,
Dennis Sylvester,
Tsu-Jae King,
Chenming Hu:
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design.
IEEE Trans. VLSI Syst. 13(1): 158-162 (2005) |
| 6 | EE | Yu Cao,
Xiao-dong Yang,
Xuejue Huang,
Dennis Sylvester:
Switch-factor based loop RLC modeling for efficient timing analysis.
IEEE Trans. VLSI Syst. 13(9): 1072-1078 (2005) |
| 2003 |
|---|
| 5 | EE | Yu Cao,
Xiao-dong Yang,
Xuejue Huang,
Dennis Sylvester:
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.
ICCAD 2003: 848-854 |
| 4 | EE | Yu Cao,
Chenming Hu,
Xuejue Huang,
Andrew B. Kahng,
Igor L. Markov,
Michael Oliver,
Dirk Stroobandt,
Dennis Sylvester:
Improved a priori interconnect predictions and technology extrapolation in the GTX system.
IEEE Trans. VLSI Syst. 11(1): 3-14 (2003) |
| 2002 |
|---|
| 3 | EE | Yu Cao,
Xuejue Huang,
N. H. Chang,
Shen Lin,
O. Sam Nakagawa,
Weize Xie,
Dennis Sylvester,
Chenming Hu:
Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.
IEEE Trans. VLSI Syst. 10(6): 799-805 (2002) |
| 2001 |
|---|
| 2 | EE | Yu Cao,
Xuejue Huang,
Chenming Hu,
Norman Chang,
Shen Lin,
O. Sam Nakagawa,
Weize Xie:
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.
ISQED 2001: 185-190 |
| 2000 |
|---|
| 1 | | Yu Cao,
Chenming Hu,
Xuejue Huang,
Andrew B. Kahng,
Sudhakar Muddu,
Dirk Stroobandt,
Dennis Sylvester:
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design.
ICCAD 2000: 56-61 |
