| 2003 |
|---|
| 10 | EE | Ki-Wook Kim,
Seong-Ook Jung,
Unni Narayanan,
C. L. Liu,
Sung-Mo Kang:
Noise-aware interconnect power optimization in domino logic synthesis.
IEEE Trans. VLSI Syst. 11(1): 79-89 (2003) |
| 2002 |
|---|
| 9 | EE | Unni Narayanan,
Ki-Seok Chung,
Taewhan Kim:
Enhanced bus invert encodings for low-power.
ISCAS (5) 2002: 25-28 |
| 2000 |
|---|
| 8 | EE | Ki-Wook Kim,
Unni Narayanan,
Sung-Mo Kang:
Domino logic synthesis minimizing crosstalk.
DAC 2000: 280-285 |
| 7 | EE | Ki-Wook Kim,
Seong-Ook Jung,
Unni Narayanan,
C. L. Liu,
Sung-Mo Kang:
Noise-aware power optimization for on-chip interconnect.
ISLPED 2000: 108-113 |
| 6 | EE | Sungpack Hong,
Taewhan Kim,
Unni Narayanan,
Ki-Seok Chung:
Decomposition of Bus-Invert Coding for Low-Power I/O.
Journal of Circuits, Systems, and Computers 10(1-2): 101-112 (2000) |
| 1999 |
|---|
| 5 | EE | Priyadarshan Patra,
Unni Narayanan:
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits.
DAC 1999: 379-384 |
| 4 | | Unni Narayanan,
Georgios I. Stamoulis,
Rabindra K. Roy:
Characterizing Individual Gate Power Sensitivity in Low Power Design.
VLSI Design 1999: 625- |
| 1998 |
|---|
| 3 | EE | Unni Narayanan,
Peichen Pan,
C. L. Liu:
Low power logic synthesis under a general delay model.
ISLPED 1998: 209-214 |
| 1997 |
|---|
| 2 | EE | Unni Narayanan,
C. L. Liu:
Low power logic synthesis for XOR based circuits.
ICCAD 1997: 570-574 |
| 1 | EE | Unni Narayanan,
Hon Wai Leong,
Ki-Seok Chung,
Chien-Liang Liu:
Low power multiplexer decomposition.
ISLPED 1997: 269-274 |
