2003 |
3 | EE | Rajiv V. Joshi,
Ching-Te Chuang,
S. K. H. Fung,
Fari Assaderaghi,
Melanie Sherony,
I. Yang,
Ghavam V. Shahidi:
PD/SOI SRAM performance in presence of gate-to-body tunneling current.
IEEE Trans. VLSI Syst. 11(6): 1106-1113 (2003) |
1999 |
2 | EE | Fari Assaderaghi:
Circuit styles and strategies for CMOS VLSI design on SOI.
ISLPED 1999: 282-287 |
1997 |
1 | EE | Jim Burr,
Anantha Chandrakasan,
Fari Assaderaghi,
Francky Catthoor,
Frank Fox,
Dave Greenhill,
Deo Singh,
Jim Sproch:
Low power design without compromise (panel).
ISLPED 1997: 293-294 |