| 2001 |
|---|
| 9 | EE | Jin-fuw Lee,
Daniel L. Ostapko,
Jeffery Soreff,
C. K. Wong:
On the Signal Bounding Problem in Timing Analysis.
ICCAD 2001: 507-514 |
| 1996 |
|---|
| 8 | EE | Jin-fuw Lee,
Donald T. Tang,
Chak-Kuen Wong:
A timing analysis algorithm for circuits with level-sensitive latches.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 535-543 (1996) |
| 1995 |
|---|
| 7 | EE | Jin-fuw Lee,
Donald T. Tang:
An Algorithm for Incremental Timing Analysis.
DAC 1995: 696-701 |
| 1994 |
|---|
| 6 | EE | Jin-fuw Lee,
Donald T. Tang,
C. K. Wong:
A timing analysis algorithm for circuits with level-sensitive latches.
ICCAD 1994: 743-748 |
| 1992 |
|---|
| 5 | EE | Jin-fuw Lee,
Donald T. Tang:
HIMALAYAS - a hierarchical compaction system with a minimized constraint set.
ICCAD 1992: 150-157 |
| 4 | EE | Jin-fuw Lee,
Chak-Kuen Wong:
A performance-aimed cell compactor with automatic jogs.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1495-1507 (1992) |
| 1991 |
|---|
| 3 | | Jin-fuw Lee:
A Layout Compaction Algorithm with Multiple Grid Constraints.
ICCD 1991: 30-33 |
| 1988 |
|---|
| 2 | EE | Jin-fuw Lee:
A new framework of design rules for compaction of VLSI layouts.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(11): 1195-1204 (1988) |
| 1987 |
|---|
| 1 | EE | Jin-fuw Lee,
Donald T. Tang:
VLSI Layout Compaction with Grid and Mixed Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 903-910 (1987) |
