| 1999 |
|---|
| 8 | EE | Ashok Vittal,
Lauren Hui Chen,
Malgorzata Marek-Sadowska,
Kai-Ping Wang,
Sherry Yang:
Modeling Crosstalk in Resistive VLSI Interconnections.
VLSI Design 1999: 470-475 |
| 7 | EE | Ashok Vittal,
Lauren Hui Chen,
Malgorzata Marek-Sadowska,
Kai-Ping Wang,
Sherry Yang:
Crosstalk in VLSI interconnections.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1817-1824 (1999) |
| 1997 |
|---|
| 6 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Crosstalk reduction for VLSI.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 290-298 (1997) |
| 5 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Low-power buffered clock tree design.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 965-975 (1997) |
| 1996 |
|---|
| 4 | EE | Ashok Vittal,
Hein Ha,
Forrest Brewer,
Malgorzata Marek-Sadowska:
Clock skew optimization for ground bounce control.
ICCAD 1996: 395-399 |
| 1995 |
|---|
| 3 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Power Optimal Buffered Clock Tree Design.
DAC 1995: 497-502 |
| 2 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Power Distribution Topology Design.
DAC 1995: 503-507 |
| 1994 |
|---|
| 1 | EE | Ashok Vittal,
Malgorzata Marek-Sadowska:
Minimal Delay Interconnect Design Using Alphabetic Trees.
DAC 1994: 392-396 |
