2003 |
6 | EE | Ludovico de Souza,
Philip Ryan,
Jason Crawford,
Kevin Wong,
Gregory B. Zyner,
Tom McDermott:
Prototyping for the Concurrent Development.
FPL 2003: 51-60 |
1995 |
5 | | Dale Greenley,
J. Bauman,
D. Chang,
Dennis Chen,
R. Eltejaein,
P. Ferolito,
P. Fu,
Robert B. Garner,
D. Greenhill,
H. Grewal,
Kalon Holdbrook,
B. Kim,
Leslie Kohn,
H. Kwan,
M. Levitt,
Guillermo Maturana,
D. Mrazek,
Chitresh Narasimhaiah,
Kevin Normoyle,
N. Parveen,
P. Patel,
A. Prabhu,
Marc Tremblay,
Michelle Wong,
L. Yang,
Krishna Yarlagadda,
Robert K. Yu,
Robert Yung,
Gregory B. Zyner:
UltraSPARC: The Next Generation Superscalar 64-bit SPARC.
COMPCON 1995: 442-451 |
4 | | Leslie Kohn,
Guillermo Maturana,
Marc Tremblay,
A. Prabhu,
Gregory B. Zyner:
The Visual Instruction Set (VIS) in UltraSPARC.
COMPCON 1995: 462-469 |
3 | EE | A. Cao,
A. Adalal,
J. Bauman,
P. Delisle,
P. Dedood,
P. Donehue,
M. Dell'OcaKhouja,
T. Doan,
Manjunath Doreswamy,
P. Ferolito,
O. Geva,
D. Greenhill,
S. Gopaladhine,
J. Irwin,
L. Lev,
J. MacDonald,
M. Ma,
Samir Mitra,
P. Patel,
A. Prabhu,
R. Puranik,
S. Rozanski,
N. Ross,
P. Saggurti,
S. Simovich,
R. Sunder,
B. Sur,
W. Vercruysse,
Michelle Wong,
P. Yip,
Robert K. Yu,
J. Zhou,
Gregory B. Zyner:
CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems Inc.
DAC 1995: 19-22 |
2 | EE | Robert K. Yu,
Gregory B. Zyner:
167 MHz Radix-4 Floating Point Multiplier.
IEEE Symposium on Computer Arithmetic 1995: 149-154 |
1 | EE | J. Arjun Prabhu,
Gregory B. Zyner:
167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages.
IEEE Symposium on Computer Arithmetic 1995: 155-162 |