2008 |
23 | EE | Paul D. Franzon,
W. Rhett Davis,
Michael Steer,
Steve Lipa,
Eun Chu Oh,
Thor Thorolfsson,
Samson Melamed,
Sonali Luniya,
Tad Doxsee,
Stephen Berkeley,
Ben Shani,
Kurt Obermiller:
Design and CAD for 3D integrated circuits.
DAC 2008: 668-673 |
2007 |
22 | EE | Meeta Yadav,
Ashwini Venkatachaliah,
Paul D. Franzon:
Hardware Architecture of a Parallel Pattern Matching Engine.
ISCAS 2007: 1369-1372 |
21 | EE | Liang Zhang,
J. M. Wilson,
Rizwan Bashirullah,
Lei Luo,
Jian Xu,
Paul D. Franzon:
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses.
IEEE Trans. VLSI Syst. 15(2): 231-236 (2007) |
2005 |
20 | EE | Liang Zhang,
John Wilson,
Rizwan Bashirullah,
Lei Luo,
Jian Xu,
Paul D. Franzon:
Driver pre-emphasis techniques for on-chip global buses.
ISLPED 2005: 186-191 |
19 | EE | Numan Sadi Dogan,
Paul D. Franzon,
Wentai Liu:
Impact of an SoC Research Project on Microelectronics Education: A Case Study.
MSE 2005: 33-34 |
18 | EE | W. Rhett Davis,
John Wilson,
Stephen Mick,
Jian Xu,
Hao Hua,
Christopher Mineo,
Ambarish M. Sule,
Michael Steer,
Paul D. Franzon:
Demystifying 3D ICs: The Pros and Cons of Going Vertical.
IEEE Design & Test of Computers 22(6): 498-510 (2005) |
17 | EE | Monther Aldwairi,
Thomas M. Conte,
Paul D. Franzon:
Configurable string matching hardware for speeding up intrusion detection.
SIGARCH Computer Architecture News 33(1): 99-107 (2005) |
2004 |
16 | EE | Liang Zhang,
Wentai Liu,
Rizwan Bashirullah,
John Wilson,
Paul D. Franzon:
Simplified delay design guidelines for on-chip global interconnects.
ACM Great Lakes Symposium on VLSI 2004: 29-32 |
15 | EE | J. A. Palmer,
James F. Mulling,
Brian Dessent,
Edward Grant,
Jeffrey W. Eischen,
Alexei Gruverman,
A. I. Kingon,
Paul D. Franzon:
The Design, Fabrication, and Characterization of Millimeter Scale Motors for Miniature Direct Drive Robots.
ICRA 2004: 4668-4673 |
2001 |
14 | EE | Andreas Kuehlmann,
Robert W. Dutton,
Paul D. Franzon,
Seth Copen Goldstein,
Philip Luekes,
Eric Parker,
Thomas N. Theis:
Will Nanotechnology Change the Way We Design and Verify Systems? (Panel).
ICCAD 2001: 174 |
1999 |
13 | EE | B. E. Duewer,
J. M. Wilson,
D. A. Winick,
Paul D. Franzon:
MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications.
ARVLSI 1999: 369-377 |
12 | EE | Paul D. Franzon,
Mark Basel,
Aki Fujimara,
Sharad Mehrotra,
Ron Preston,
Robin C. Sarma,
Marty Walker:
Parasitic Extraction Accuracy - How Much is Enough?
DAC 1999: 429 |
11 | EE | Mouna Nakkar,
David G. Bentlage,
John Harding,
David Schwartz,
Paul D. Franzon,
Thomas M. Conte:
Dynamically Programmable Cache Evaluation and Virtualization.
FPGA 1999: 246 |
10 | EE | Toby Schaffer,
Andy Stanaski,
Alan Glaser,
Paul D. Franzon:
The NCSU Cadence Design Kit for IC Fabrication through MOSIS.
MSE 1999: 88-89 |
1997 |
9 | EE | Mir Azam,
Paul D. Franzon,
Wentai Liu:
Low power data processing by elimination of redundant computations.
ISLPED 1997: 259-264 |
8 | EE | Hong-Yean Hsieh,
Wentai Liu,
Paul D. Franzon,
Ralph K. Cavin III:
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.
VLSI Signal Processing 16(2-3): 131-147 (1997) |
1995 |
7 | EE | Sharad Mehrotra,
Paul D. Franzon,
Michael Steer:
Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs.
DAC 1995: 381-387 |
1994 |
6 | EE | Sharad Mehrotra,
Paul D. Franzon,
Wentai Liu:
Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits.
DAC 1994: 36-40 |
1993 |
5 | | Todd A. Cook,
Paul D. Franzon,
Edwin A. Harcourt,
Thomas K. Miller III:
System-Level Specification of Instruction Sets.
ICCD 1993: 552-557 |
4 | | Paul D. Franzon,
Robert J. Evans:
A Multichip Module Design Process for Notebook Computers.
IEEE Computer 26(4): 41-49 (1993) |
1992 |
3 | EE | Ajay Dholakia,
T. M. Lee,
Donald L. Bitzer,
Mladen A. Vouk,
L. Wang,
Paul D. Franzon:
An efficient table-driven decoder for one-half rate convolutional codes.
ACM Southeast Regional Conference 1992: 116-123 |
2 | EE | Paul D. Franzon,
Slobodan Simovich,
Michael Steer,
Mark Basel,
Sharad Mehrotra,
Tom Mills:
Tools to Aid in Wiring Rule Generation for High Speed Interconnects.
DAC 1992: 466-471 |
1990 |
1 | EE | D. Bout,
Paul D. Franzon,
J. Paulos,
T. Miller,
W. Snyder,
T. Nagle,
Wentai Liu:
Scalable VLSI implementations for neural networks.
VLSI Signal Processing 1(4): 367-385 (1990) |