2008 | ||
---|---|---|
51 | EE | Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberlain: Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs. ASAP 2008: 191-196 |
50 | EE | Joseph M. Lancaster, Ron Cytron, Roger D. Chamberlain: Understanding the performance of streaming applications deployed on hybrid systems. IPDPS 2008: 1-5 |
49 | EE | Praveen Krishnamurthy, Roger D. Chamberlain: Analytic performance models for bounded queueing systems. IPDPS 2008: 1-8 |
48 | EE | Roger D. Chamberlain, Joseph M. Lancaster, Ron K. Cytron: Visions for application development on hybrid computing systems. Parallel Computing 34(4-5): 201-216 (2008) |
47 | EE | Roger D. Chamberlain, Joseph M. Lancaster, Ron K. Cytron: Visions for application development on hybrid computing systems. Parallel Computing 34(4-5): 201-216 (2008) |
46 | EE | Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Brandon Harris, Roger D. Chamberlain: Mercury BLASTP: Accelerating Protein Sequence Alignment. TRETS 1(2): (2008) |
2007 | ||
45 | EE | Richard Hough, Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, John W. Lockwood, Jason E. Fritts: Empirical performance assessment using soft-core processors on reconfigurable hardware. Experimental Computer Science 2007: 18 |
44 | EE | Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain: FPGA-accelerated seed generation in Mercury BLASTP. FCCM 2007: 95-106 |
43 | EE | Brandon Harris, Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain: A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP. FPL 2007: 765-769 |
42 | EE | Arpith C. Jacob, Joseph M. Lancaster, Jeremy D. Buhler, Roger D. Chamberlain: Preliminary results in accelerating profile HMM search on FPGAs. IPDPS 2007: 1-8 |
41 | EE | Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, Roger D. Chamberlain: A Federated Simulation Environment for Hybrid Systems. PADS 2007: 198-210 |
40 | EE | Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, Jeremy Buhler, Saurabh Gayen, Patrick Crowley, James H. Buckley: Application development on hybrid systems. SC 2007: 50 |
39 | EE | Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Arpith C. Jacob, Joseph M. Lancaster: Biosequence Similarity Search on the Mercury System. VLSI Signal Processing 49(1): 101-121 (2007) |
2006 | ||
38 | EE | Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, Young H. Cho: Scalable Softcore Vector Processor for Biosequence Applications. FCCM 2006: 295-296 |
37 | EE | Rahul P. Maddimsetty, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Brandon Harris: Accelerator design for protein sequence HMM search. ICS 2006: 288-296 |
36 | EE | Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain, John W. Lockwood: Automatic application-specific microarchitecture reconfiguration. IPDPS 2006 |
35 | EE | Gary Stiehr, Roger D. Chamberlain: Improving cluster utilization through intelligent processor sharing. IPDPS 2006 |
34 | EE | Roger D. Chamberlain, Ron K. Cytron, Jason E. Fritts, John W. Lockwood: Vision for liquid architecture. IPDPS 2006 |
2005 | ||
33 | EE | Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip H. Jones: Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory. MSE 2005: 97-98 |
32 | EE | Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood: Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures. International Journal of Parallel Programming 33(2-3): 115-136 (2005) |
31 | EE | Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy, Abhijit Mahajan: VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance. VLSI Signal Processing 40(1): 57-72 (2005) |
2004 | ||
30 | EE | Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster: Biosequence Similarity Search on the Mercury System. ASAP 2004: 365-375 |
29 | EE | Mark A. Franklin, Roger D. Chamberlain, Michael Henrichs, Berkley Shands, Jason White: An Architecture for Fast Processing of Large Unstructured Data Sets. ICCD 2004: 280-287 |
28 | EE | Qiong Zhang, Roger D. Chamberlain, Ronald S. Indeck, Benjamin M. West, Jason White: Massively Parallel Data Mining Using Reconfigurable Hardware: Approximate String Matching. IPDPS 2004 |
2003 | ||
27 | EE | Roger D. Chamberlain, Eric Hemmeter, Robert Morley, Jason White: Modeling the Power Consumption of Audio Signal Processing Computations Using Customized Numerical Representations. Annual Simulation Symposium 2003: 249-255 |
26 | EE | Praveen Krishnamurthy, Mark A. Franklin, Roger D. Chamberlain: Dynamic Reconfiguration of an Optical Interconnect. Annual Simulation Symposium 2003: 89-97 |
2002 | ||
25 | EE | Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy: Optical Network Reconfiguration for Signal Processing Applications. ASAP 2002: 344- |
24 | EE | Michael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O'Sullivan, Mark A. Franklin: Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System. ASAP 2002: 391- |
23 | EE | Roger D. Chamberlain, Ch'ng Shi Baw, Mark A. Franklin, Christopher Hackmann, Praveen Krishnamurthy, Abhijit Mahajan, Michael Wrighton: Evaluating the Performance of Photonic Interconnection Networks. Annual Simulation Symposium 2002: 209-218 |
22 | EE | Jason E. Fritts, Roger D. Chamberlain: Breaking the Memory Bottleneck with an Optical Data Path. Annual Simulation Symposium 2002: 352- |
21 | EE | Roger D. Chamberlain, Mark A. Franklin, Ch'ng Shi Baw: Gemini: An Optical Interconnection Network for Parallel Processing. IEEE Trans. Parallel Distrib. Syst. 13(10): 1038-1055 (2002) |
2001 | ||
20 | EE | Bradley L. Noble, J. Cris Wade, Roger D. Chamberlain: Performance Predictions for Speculative, Synchronous, VLSI Logic Simulation. Annual Simulation Symposium 2001: 56-64 |
19 | Roger D. Chamberlain, Mark A. Franklin, Abhijit Mahajan: VLSI Photonic Ring Interconnect for Embedded Multicomputers: Architecture and Performance. ISCA PDCS 2001: 351-358 | |
2000 | ||
18 | EE | Bradley L. Noble, Roger D. Chamberlain: Analytic performance model for speculative, synchronous, discrete-event simulation. PADS 2000: 30-44 |
1999 | ||
17 | EE | Bradley L. Noble, Roger D. Chamberlain: Performance Model for Speculative Simulation using Predictive Optimism. HICSS 1999 |
16 | EE | Ch'ng Shi Baw, Roger D. Chamberlain, Mark A. Franklin: Fair Scheduling in an Optical Interconnection Network. MASCOTS 1999: 56- |
1996 | ||
15 | EE | Gregory D. Peterson, Roger D. Chamberlain: Parallel application performance in a shared resource environment. Distributed Systems Engineering 3(1): 9-19 (1996) |
1995 | ||
14 | EE | Roger D. Chamberlain: Parallel Logic Simulation of VLSI Systems. DAC 1995: 139-143 |
13 | EE | Bradley L. Noble, Gregory D. Peterson, Roger D. Chamberlain: Performance of synchronous parallel discrete-event simulation. HICSS (2) 1995: 185-186 |
12 | EE | Gregory D. Peterson, Roger D. Chamberlain: Stealing cycles: Can we get along? HICSS (2) 1995: 422-441 |
11 | EE | Roger D. Chamberlain, Gregory D. Peterson, Mark A. Franklin, Michael A. Province: Genetic epidemiology, parallel algorithms, and workstation networks. HICSS (5) 1995: 101-111 |
10 | EE | George Varghese, Roger D. Chamberlain, William E. Weihl: Deriving Global Virtual Time Algorithms from Conservative Simulation Protocols. Inf. Process. Lett. 54(2): 121-126 (1995) |
1994 | ||
9 | Mary L. Bailey, Jack V. Briner Jr., Roger D. Chamberlain: Parallel Logic Simulation of VLSI Systems. ACM Comput. Surv. 26(3): 255-294 (1994) | |
1993 | ||
8 | Gregory D. Peterson, Roger D. Chamberlain: Performance of a Globally-Clocked Parallel Simulator. ICPP 1993: 289-298 | |
7 | Roger D. Chamberlain, Mark A. Franklin: Performance Effects of Synchronization in Parallel Processors. SPDP 1993: 611-616 | |
6 | EE | Gregory D. Peterson, Roger D. Chamberlain: Exploiting lookahead in synchronous parallel simulation. Winter Simulation Conference 1993: 706-712 |
1991 | ||
5 | Roger D. Chamberlain, Mark A. Franklin: Analysis of Parallel Mixed-Mode Simulation Algorithms. IPPS 1991: 155-160 | |
4 | EE | Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin: Parallel Simulated Annealing using Speculative Computation. IEEE Trans. Parallel Distrib. Syst. 2(4): 483-494 (1991) |
1990 | ||
3 | Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin: Parallel Simulated Annealing Using Speculative Computation. ICPP (3) 1990: 286-290 | |
1986 | ||
2 | EE | Kenneth F. Wong, Mark A. Franklin, Roger D. Chamberlain, B. L. Shing: Statistics on logic simulation. DAC 1986: 13-19 |
1 | EE | Roger D. Chamberlain, Mark A. Franklin: Collecting Data About Logic Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 5(3): 405-412 (1986) |