| 2005 |
| 13 | EE | Fred Ma,
John P. Knight,
Calvin Plett:
Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms.
IEEE Trans. VLSI Syst. 13(5): 553-563 (2005) |
| 2004 |
| 12 | | Fred Ma,
John P. Knight,
Calvin Plett:
Physical Resource Binding for a Coarse Grain Reconfigurable Array.
ERSA 2004: 109-115 |
| 2002 |
| 11 | EE | Rolando Ramírez Ortiz,
John P. Knight:
Compatible cell connections for multifamily dynamic logic gates.
IEEE Trans. VLSI Syst. 10(3): 327-340 (2002) |
| 2001 |
| 10 | EE | Elie Torbey,
John P. Knight:
Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms.
IEEE Trans. VLSI Syst. 9(5): 599-607 (2001) |
| 1996 |
| 9 | EE | Raul San Martin,
John P. Knight:
Optimizing Power in ASIC Behavioral Synthesis.
IEEE Design & Test of Computers 13(2): 58-70 (1996) |
| 1995 |
| 8 | EE | Raul San Martin,
John P. Knight:
Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level.
DAC 1995: 42-47 |
| 1993 |
| 7 | | Raul San Martin,
John P. Knight:
Genetic Algorithms for the Optimization of Integrated Circuits Synthesis.
ICGA 1993: 432-438 |
| 6 | EE | Raul San Martin,
John P. Knight:
Operations research in the high-level synthesis of integrated circuits.
Computers & OR 20(8): 845-856 (1993) |
| 1989 |
| 5 | EE | Pierre G. Paulin,
John P. Knight:
Scheduling and Binding Algorithms for High-Level Synthesis.
DAC 1989: 1-6 |
| 4 | EE | Pierre G. Paulin,
John P. Knight:
Force-directed scheduling for the behavioral synthesis of ASICs.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 661-679 (1989) |
| 1987 |
| 3 | EE | Pierre G. Paulin,
John P. Knight:
Force-Directed Scheduling in Automatic Data Path Synthesis.
DAC 1987: 195-202 |
| 1986 |
| 2 | EE | Pierre G. Paulin,
John P. Knight,
Emil F. Girczyc:
HAL: a multi-paradigm approach to automatic data path synthesis.
DAC 1986: 263-270 |
| 1985 |
| 1 | EE | Emil F. Girczyc,
Raymond J. A. Buhr,
John P. Knight:
Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(2): 134-142 (1985) |