ISCAS 1999:
Orlando,
Florida,
USA - Volume 1
International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA.
IEEE 1999, ISBN 0-7803-5471-0 BibTeX
- Dorin Emil Calbaza, Yvon Savaria:
Jitter model of direct digital synthesis clock generators.
1-4
Electronic Edition (link) BibTeX
- Graham A. Jullien, Vassil S. Dimitrov, B. Li, William C. Miller, A. Lee, Majid Ahmadi:
A hybrid DBNS processor for DSP computation.
5-8
Electronic Edition (link) BibTeX
- Allan R. Dyck, S. Evenson, H. Fu, Richard F. Hobson:
User selectable feature support for an embedded processor.
9-12
Electronic Edition (link) BibTeX
- E. K. Ogoubi, Eduard Cerny:
Synthesis of checker EFSMs from timing diagram specifications.
13-18
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- Arthur T. G. Fuller, Behrouz Nowrouzian:
An exact BIBO stability condition for Bode-type variable-amplitude digital equalizers.
19-22
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- Dimitrios Kagaris, Spyros Tragoudas:
Embedded cores using built-in mechanisms.
23-26
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- Ahmed M. Shams, Magdy A. Bayoumi:
Performance evaluation of 1-bit CMOS adder cells.
27-30
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- Andreas G. Veneris, Ibrahim N. Hajj:
Correcting multiple design errors in digital VLSI circuits.
31-34
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- Gustavo R. Alves, José M. M. Ferreira:
A system verification strategy based on the BST infrastructure.
35-38
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- Seung-Wook Lee, Daeyun Shim, Yeon-Jae Jung, Dong-Yun Lee, Chang-Hyun Kim, Wonchan Kim:
A load-adaptive, low switching-noise data output buffer.
39-42
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- Hanan A. Mahmoud, Magdy A. Bayoumi:
A 10-transistor low-power high-speed full adder cell.
43-46
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- Chung-Yu Wu, Yu-Yee Liow:
A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs.
47-50
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- Chin-Liang Wang, Ching-Hsien Chang:
A novel DHT-based FFT/IFFT processor for ADSL transceivers.
51-54
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- K. Bacrania, Tzi-Hsiung Shu:
A CMOS 10 b 60 Msample/s ADC with ultra fast gain control.
55-58
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- Sven Simon, Marek Wróblewski:
Low power datapath design using transformation similar to temporal localization of SFGs.
59-61
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- Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.:
Improved-Booth encoding for low-power multipliers.
62-65
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- Ashok Kumar, Magdy A. Bayoumi, Raghava V. Cherabuddi:
Minimizing switchings of the function units through binding for low power.
66-69
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- Imed Ben Dhaou, Hannu Tenhunen:
Combinatorial architectural level power optimization for a class of orthogonal transforms.
70-75
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- C. Chakrabarti, D. Gaitonde:
Instruction level power model of microcontrollers.
76-79
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- Mark S. Bright, Tughrul Arslan:
Multi-objective design strategy for high-level low power design of DSP systems.
80-83
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- Leilei Song, Keshab K. Parhi:
Low-energy software Reed-Solomon codecs using specialized finite field datapath and division-free Berlekamp-Massey algorithm.
84-89
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- Christian V. Schimpfle, Sven Simon, Josef A. Nossek:
Device level based cell modeling for fast power estimation.
90-93
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- Parag K. Lala, A. L. Burress:
A technique for designing self-checking logic for FPGAs.
94-96
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- W. Quddus, Abhijit Jas, Nur A. Touba:
Configuration self-test in FPGA-based reconfigurable systems.
97-100
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- Kamran Zarrineh, Shambhu J. Upadhyaya:
A design for test perspective on memory synthesis.
101-104
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- K. Raahernifar, M. Ahmadi:
On-line IDDQ fault testing for CMOS/BiCMOS logic families.
105-109
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- Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, P. Teixeira, M. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
110-113
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- Paulo F. Flores, Horácio C. Neto, K. Chakrabarty, João P. Marques Silva:
Test pattern generation for width compression in BIST.
114-118
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- P. K. Jaini, Nur A. Touba:
Observing test response of embedded cores through surrounding logic.
119-123
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- R. A. Said:
Internal testing of integrated circuits by noncontact sampling electrostatic force microscopy using pulse width modulation technique.
124-128
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- Robert C. Chang, Lung-Chih Kuo, Chih-Yuan Hsieh:
VLSI implementation of a multicast ATM switch.
129-132
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- Lihong Jia, Yonghong Gao, Jouni Isoaho, Hannu Tenhunen:
Design of a super-pipelined Viterbi decoder.
133-136
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- Chi-Ying Tsui, R. S.-K. Cheng, C. Ling:
Low power ACS unit design for the Viterbi decoder [CDMA wireless systems].
137-140
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- Li-minn Ang, Hon Nin Cheung, Kamran Eshraghian:
VLSI decoder architecture for embedded zerotree wavelet algorithm.
141-144
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- Guoqing Zhang, M. Talley, Wael M. Badawy, Michael Weeks, Magdy A. Bayoumi:
A low power prototype for a 3D discrete wavelet transform processor.
145-148
Electronic Edition (link) BibTeX
- S. Masupe, T. Arslan:
Low power DCT implementation approach for VLSI DSP processors.
149-152
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- Jie Chen, K. J. Ray Liu:
Cost-effective low-power architectures of video coding systems.
153-156
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- Mladen Berekovic, K. Jacob, Peter Pirsch:
Architecture of a hardware module for MPEG-4 shape decoding.
157-160
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- C.-C. Wang, C. J. Huang, P.-M. Lee:
A comparison of two alternative architectures of digital ratioed compressor design for inner product processing.
161-164
Electronic Edition (link) BibTeX
- R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
Power implications of precision limited arithmetic in floating point FIR filters.
165-168
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- Gustavo R. Alves, Tito G. B. Amaral, José M. M. Ferreira:
Board-level prototype validation: a built-in controller and extended BST architecture.
169-172
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- Shyue-Kung Lu, Cheng-Wen Wu:
A novel approach to testing LUT-based FPGAs.
173-177
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- Bin Zhang, K. J. Chen, Ruan Gang, Richard M. M. Chen:
A novel RTD-HEMT-RTD structure based on simulations.
178-181
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- M. Fedeli, C. Vacchi:
A receiver for stardard IEEE 1596-1992 scalable coherent interface.
182-185 BibTeX
- P. J. Amantia, M. J. Kane, E. A. Kimball, S. L. Garverick:
A mixed-signal IC for a semi-implantable hearing aid.
186-189
Electronic Edition (link) BibTeX
- E. Andre, G. Martel, P. Senn:
Digital I/Q demodulation and digital filtering for a DAB receiver.
190-193
Electronic Edition (link) BibTeX
- Mark Clements, Kasin Vichienchom, Wentai Liu, C. Hughes, E. McGucken, C. DeMarco, J. Mueller, Mark S. Humayun, E. De Juan, James D. Weiland, R. Greenberg:
An implantable power and data receiver and neuro-stimulus chip for a retinal prosthesis system.
194-197
Electronic Edition (link) BibTeX
- M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, G. A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis:
The VLSI implementation of a baseband receiver for DECT-based portable applications.
198-201
Electronic Edition (link) BibTeX
- Juha Häkkinen, Timo Rahkonen, Juha Kostamovaara:
A frequency hopping synthesizer IC for IF and RF applications.
202-205
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- E. Westesson, Lars Sundström:
A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers.
206-209
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- Wuping Chen, Hongwei Duan, S. H. Jones:
Integrated 1.2 um CMOS photodiodes, transimpedance amplifier, 12 bits A/D converter, and DSP interface for microinstrument applications.
210-213
Electronic Edition (link) BibTeX
- Chang-Ki Kwon, Kwyro Lee:
A low-power minimum distance 1D-search engine using hybrid digital/analog circuit techniques.
214-217
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- J. C. Bernier, G. D. Croft, W. R. Young:
A process independent ESD design methodology.
218-221
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- Lap-Pui Chau, Nam Ling, Gunnar Hovden, Hui Lan, Hon-Cheong Ng, Keng-Pang Lim:
A real-time realization of MPEG-4 video decoder.
222-225
Electronic Edition (link) BibTeX
- Seung-Moon Yoo, Sung-Mo Kang:
CMOS Pass-gate No-race Charge-recycling Logic (CPNCL).
226-229
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- A. M. Fahim, Mohamed I. Elmasry:
A Low-Voltage High-Performance Differential Static Logic (LVDSL) family.
230-233
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- Abdoul Rjoub, Odysseas G. Koufopavlou:
Low voltage swing gates for low power consumption.
234-237
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- Hongchin Lin, Kai-Hsun Chang, Shyh-Chyi Wong:
Novel high positive and negative pumping circuits for low supply voltage.
238-241
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- Radu M. Secareanu, Eby G. Friedman, Juan Becerra, Scott Warner:
A universal CMOS voltage interface circuit.
242-245
Electronic Edition (link) BibTeX
- Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone:
Power reduction through iterative gate sizing and voltage scaling.
246-249
Electronic Edition (link) BibTeX
- Wen-Tsong Shiue, Chaitali Chakrabarti:
Memory exploration for low power embedded systems.
250-253
Electronic Edition (link) BibTeX
- Ching-Rong Chang, Jinn-Shyan Wang:
A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM.
254-257
Electronic Edition (link) BibTeX
- P. Palojarvi, T. Ruotsalainen, Juha Kostamovaara:
A new approach to avoid walk error in pulsed laser rangefinding.
258-261
Electronic Edition (link) BibTeX
- M. Kaneko:
Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power.
262-265
Electronic Edition (link) BibTeX
- R. R.-B. Sheen, S. Wang, Oscal T.-C. Chen, Ruey-Liang Ma:
Power consumption of a 2's complement adder minimized by effective dynamic data ranges.
266-269
Electronic Edition (link) BibTeX
- Hwang-Cherng Chow:
Bidirectional buffer for mixed voltage applications.
270-273
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- Edgar F. M. Albuquerque, Manuel M. Silva:
Current-balanced logic for mixed-signal IC's.
274-277
Electronic Edition (link) BibTeX
- Elvi Räisänen-Ruotsalainen, Timo Rahkonen, Juha Kostamovaara:
A BiCMOS time-to-digital converter with 30 ps resolution.
278-281
Electronic Edition (link) BibTeX
- A. Tezel, T. Akin:
A low-power switched-current algorithmic A/D converter.
282-285
Electronic Edition (link) BibTeX
- George Theodoridis, S. Theoharis, Dimitrios Soudris, Thanos Stouraitis, Constantinos E. Goutis:
An efficient probabilistic method for logic circuits using real delay gate model.
286-289
Electronic Edition (link) BibTeX
- Yumin Zhang, Xiaobo Hu, Danny Z. Chen:
Low energy register allocation beyond basic blocks.
290-293
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- Chaeryung Park, Taewhan Park, C. L. Liu:
An efficient data path synthesis algorithm for behavioral-level power optimization.
294-297
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- Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.:
A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.
298-301
Electronic Edition (link) BibTeX
- John M. Emmert, Dinesh Bhatia:
Fast timing driven placement using tabu search.
302-305
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- Wai-Kwong Lee, Chi-Ying Tsui:
Finite state machine partitioning for low power.
306-309
Electronic Edition (link) BibTeX
- Chingwei Yeh, Yin-Shuin Kang:
A simulated annealing based method supporting dual supply voltages in standard cell placement.
310-313
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- A. El-Aboudi, El Mostapha Aboulhamid:
An algorithm for the verification of timing diagrams realizability.
314-317
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- Jer-Sheng Chen, P. Banerjee:
Parallel construction algorithms for BDDs.
318-322
Electronic Edition (link) BibTeX
- Jinsung Park, J. A. Tabler, Martin A. Brooke, Nan M. Jokerst, D. Scott Wills:
Adaptive digital bias control for an optical receiver and transmitter.
323-326
Electronic Edition (link) BibTeX
- J. J. Chang, Myunghee Lee, Sungyong Jung, Martin A. Brooke, Nan M. Jokerst, D. Scott Wills:
Fully differential current-input CMOS amplifier front-end suppressing mixed signal substrate noise for optoelectronic applications.
327-330
Electronic Edition (link) BibTeX
- T. Yalcin, N. Ismailoglu:
Design of a fully-static differential low-power CMOS flip-flop.
331-333
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- Mark Vesterbacka:
A robust differential scan flip-flop.
334-337
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- Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda:
vMOS-based sorters for multiplier implementations.
338-341
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- Antonio J. López-Martín, Alfonso Carlosena:
Geometric-mean based current-mode CMOS multiplier/divider.
342-345
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- Pietro Andreani, Lars Sundström, N. Karlsson, M. Svensson:
A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier.
346-349
Electronic Edition (link) BibTeX
- Majid Sarrafzadeh, Salil Raje:
Scheduling with multiple voltages under resource constraints.
350-353
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- Ali Manzak, Chaitali Chakrabarti:
A low power scheduling scheme with resources operating at multiple voltages.
354-357
Electronic Edition (link) BibTeX
- Gangadhar Konduri, James Goodman, Anantha Chandrakasan:
Energy efficient software through dynamic voltage scheduling.
358-361
Electronic Edition (link) BibTeX
- Gang Qu, Darko Kirovski, Miodrag Potkonjak, Mani B. Srivastava:
Energy minimization of system pipelines using multiple voltages.
362-365
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- Kaushik Roy, Liqiong Wei, Zhanping Chen:
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.
366-370
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- Ashok Kumar, Magdy A. Bayoumi:
Multiple voltage-based scheduling methodology for low power in the high level synthesis.
371-374
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- P. Acco, Michael Peter Kennedy, C. Mira, B. Morley, B. Frigyik:
Behavioral modeling of charge pump phase locked loops.
375-378
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- Chip-Hong Chang, Bogdan J. Falkowski:
Reed-Muller weight and literal vectors for NPN classification.
379-382
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- Bogdan J. Falkowski, Chip-Hong Chang:
Optimization of partially-mixed-polarity Reed-Muller expansions.
383-386
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- Wolfgang Günther, Rolf Drechsler:
Minimization of BDDs using linear transformations based on evolutionary techniques.
387-390
Electronic Edition (link) BibTeX
- Malgorzata Chrzanowska-Jeske:
Regular symmetric arrays for non-symmetric functions.
391-394
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- A. Crews, F. Brewer:
Shape-based sequential machine analysis.
395-399
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- K. C. Chang, C. A. Lomasney:
Obsolete integrated circuit replacement methodology using advanced electronic design automation technology.
400-403
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- L. Ivanov, R. Nunna, S. Bloom:
Modeling and analysis of noniterated systems: an approach based upon series-parallel posets.
404-406
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- Gábor Hosszú, Ferenc Kovács, L. Varga:
Design procedure based on VHDL language transformations.
407-410
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- Rolf Drechsler, Marc Herbstritt, Bernd Becker:
Grouping heuristics for word-level decision diagrams.
411-414
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- Kenneth Francken, Georges G. E. Gielen:
Methodology for analog technology porting including performance tuning.
415-418
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- Ting Wu, Say Wei Foo:
An efficient method for parametric yield gradient estimation.
419-422
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- D. Torres, J. Gonzalez, M. Guzman, L. Nunez:
A new bus assignment in a designed shared bus switch fabric.
423-426
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- D. Torres, A. Larios, M. Guzman:
Routing chip based on a modified trie for ATM, IP and Ethernet.
427-430
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- Huimin Xia, K. Bataineh, M. Hassoun, J. Kryzak:
A mixed-signal behavioral level implementation of 1000BASE-X physical layer for gigabit Ethernet.
431-434
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- Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates.
435-438
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- C.-C. Wang, C. J. Huang, G.-C. Lin:
A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library.
439-442
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- B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois:
Development of a high performance TSPC library for implementation of large digital building blocks.
443-446
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- Louis Luh, John Choma Jr., Jeffrey T. Draper:
A self-sensing tristate pad driver for control signals of multiple bus controllers.
447-450
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- Vassilis Paliouras, Thanos Stouraitis:
Novel high-radix residue number system multipliers and adders.
451-454
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- Shen-Fu Hsiao:
A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations.
455-458
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- M. C. Mekhallalati, M. K. Ibrahim:
New high radix maximally-redundant signed digit adder.
459-462
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- Vicente Baena Lecuyer, M. A. Aguirre, Antonio B. Torralba, Leopoldo García Franquelo, Julio Faura:
Decoder-driven switching matrices in multicontext FPGAs: area reduction and their effect on routability.
463-466
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- Jaeyoung Kwak, Sang-Sic Yoon, Hung-Jun Kwon, Kwyro Lee:
A design of the new FPGA with data path logic and run time block reconfiguration method.
467-469
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- C. E. Rabel, Mohamad Sawan:
PARC: a new pyramidal FPGA architecture based on a RISC processor.
470-473
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- Chi-Chou Kao, Yen-Tai Lai:
A routability and performance driven technology mapping algorithm for LUT based FPGA designs.
474-477
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- J. Living, Bashir M. Al-Hashimi:
Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters.
478-481
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- Javier Valls, T. Sansaloni, M. M. Peiro, Eduardo I. Boemo:
Fast FPGA-based pipelined digit-serial/parallel multipliers.
482-485
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- Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, Fred J. Taylor:
RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic.
486-489
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- William L. Freking, Keshab K. Parhi:
Parallel modular multiplication with application to VLSI RSA implementation.
490-495
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- Jen-Shiun Chiang, Jian-Kao Chen:
An efficient VLSI architecture for RSA public-key cryptosystem.
496-499
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- Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu:
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem.
500-503
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- Jyh-Huei Guo, Chin-Liang Wang, Hung-Chih Hu:
Design and implementation of an RSA public-key cryptosystem.
504-507
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- Leilei Song, Keshab K. Parhi:
Low-complexity modified Mastrovito multipliers over finite fields GF(2M).
508-512
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- Hyunman Chang, Myung Hoon Sunwoo:
A low complexity Reed-Solomon architecture using the Euclid's algorithm.
513-516
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- Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu:
An area-efficient versatile Reed-Solomon decoder for ADSL.
517-520
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- Jyh-Huei Guo, Chin-Liang Wang:
A low time-complexity, hardware-efficient bit-parallel power-sum circuit for finite fields GF(2M).
521-524
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- Hien Ha, Forrest Brewer:
Power and signal integrity improvement in ultra high-speed current mode logic.
525-528
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- Adnan Kabbani, A. J. Al-Khalili:
Dynamic CMOS noise immunity estimation in submicron regime.
529-532
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- Adnan Kabbani, A. J. Al-Khalili:
Estimation of ground bounce effects on CMOS circuits.
533-536
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- Li-Rong Zheng, Hannu Tenhunen:
Effective power and ground distribution scheme for deep submicron high speed VLSI circuits.
537-540
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- Kevin T. Tang, Eby G. Friedman:
Peak noise prediction in loosely coupled interconnect [VLSI circuits].
541-544
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- Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen:
ESD buses for whole-chip ESD protection.
545-548
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- Lei Wang, Naresh R. Shanbhag:
Noise-tolerant dynamic circuit design.
549-552
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Copyright © Sat May 16 23:25:21 2009
by Michael Ley (ley@uni-trier.de)
