ASP-DAC 1999:
Hong Kong
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, January 18-21, 1999, Wanchai, Hong Kong.
IEEE 1999 BibTeX
@proceedings{DBLP:conf/aspdac/1999,
title = {Proceedings of the 1999 Conference on Asia South Pacific Design
Automation, January 18-21, 1999, Wanchai, Hong Kong},
booktitle = {ASP-DAC},
publisher = {IEEE},
year = {1999},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Analog CAD
Physical Design 1 - Floorplanning
Design Contest
- Ju-Hyung Kim, Sung-Wook Hwang, Seung-Hoon Lee, Yong Jee:
An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications.
25-28
Electronic Edition (link) BibTeX
- Byeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee, Sang-Won Yoon:
A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications.
29-32
Electronic Edition (link) BibTeX
- Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee:
The Design of Delay Insensitive Asynchronous 16-bit Microprocessor.
33-36
Electronic Edition (link) BibTeX
- Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta:
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection.
37-40
Electronic Edition (link) BibTeX
- Li Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, Hiroaki Kunieda:
Motion Estimator LSI for MPEG2 High Level Standard.
41-44
Electronic Edition (link) BibTeX
- Jin-Kug Lee, Dong-Young Chang, Geun-Soon Kang, Seung-Hoon Lee:
A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC.
45-48
Electronic Edition (link) BibTeX
- Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim:
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony.
49-
Electronic Edition (link) BibTeX
Circuit Simulation 1
Physical Design 2 - Partitioning
Circuit Simulation 2
Physical Design 3 - Interconnection
Circuit 1 - Low-power/High-speed
Physical Design 4 - Analog,
Noise
DA for Electronic Packages
- Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang:
Technnology Mapping for Low Power.
145-148
Electronic Edition (link) BibTeX
- Maolin Tang, Kamran Eshraghian, Hon Nin Cheung:
An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing.
149-152
Electronic Edition (link) BibTeX
- Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri:
Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis.
153-156
Electronic Edition (link) BibTeX
- Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung:
Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods.
157-160
Electronic Edition (link) BibTeX
- Hidehisa Nagano, Takayuki Suyama, Akira Nagoya:
Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach.
161-164
Electronic Edition (link) BibTeX
- Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney:
A New Numerical Method for Transient Noise Analysis of Nonlinear Circuits.
165-168
Electronic Edition (link) BibTeX
- Rung-Bin Lin, Jinq-Chang Chen:
Low Power CMOS Off-Chip Drivers with Slew-rate Difference.
169-172
Electronic Edition (link) BibTeX
- Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai:
Benchmark Circuits Improve the Quality of a Standard Cell Library.
173-176
Electronic Edition (link) BibTeX
- Takashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi:
Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution.
177-180
Electronic Edition (link) BibTeX
- Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide:
Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair.
181-184
Electronic Edition (link) BibTeX
- Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau:
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits.
185-188
Electronic Edition (link) BibTeX
- Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang:
Hierarchical Floorplan Design on the Internet.
189-192
Electronic Edition (link) BibTeX
- Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihisa Yamada, Tetsuya Fujimoto, Takashi Kambe:
A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler.
193-
Electronic Edition (link) BibTeX
Circuit 2 - Multmedia chip designs
Physical Design 5 - Special Topics
Timing analysis
Physical Design 6 - Placement & Route
Circuit 3 - Analog & Mixed Circuit
Testing 1
Power Estimation/Low-power
Testing 2 - Testing and formal Verification
BDD
Systems/HW SW co-design
Behavioral/FPGA
Copyright © Sat May 16 22:58:44 2009
by Michael Ley (ley@uni-trier.de)
