| 2006 |
|---|
| 9 | EE | Thomas Eschbach,
Wolfgang Günther,
Bernd Becker:
Orthogonal Hypergraph Drawing for Improved Visibility.
J. Graph Algorithms Appl. 10(2): 141-157 (2006) |
| 2005 |
|---|
| 8 | EE | Thomas Eschbach,
Wolfgang Günther,
Bernd Becker:
Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.
VLSI Design 2005: 433-438 |
| 2004 |
|---|
| 7 | EE | Thomas Eschbach,
Wolfgang Günther,
Bernd Becker:
Orthogonal hypergraph routing for improved visibility.
ACM Great Lakes Symposium on VLSI 2004: 385-388 |
| 6 | | Thomas Eschbach,
Rolf Dreschler,
Bernd Becker:
Placement and routing optimization for circuits derived from BDDs.
ISCAS (5) 2004: 229-232 |
| 2003 |
|---|
| 5 | | Thomas Eschbach,
Wolfgang Günther,
Bernd Becker:
Cross Reduction for Orthogonal Circuit Visualization.
VLSI 2003: 107-113 |
| 4 | EE | Rolf Drechsler,
Wolfgang Günther,
Thomas Eschbach,
Lothar Linhard,
Gerhard Angst:
Recursive bi-partitioning of netlists for large number of partitions.
Journal of Systems Architecture 49(12-15): 521-528 (2003) |
| 2002 |
|---|
| 3 | EE | Rolf Drechsler,
Wolfgang Günther,
Thomas Eschbach,
Lothar Linhard,
Gerhard Angst:
Recursive Bi-Partitioning of Netlists for Large Number of Partitions.
DSD 2002: 38-44 |
| 2 | EE | Thomas Eschbach,
Wolfgang Günther,
Rolf Drechsler,
Bernd Becker:
Crossing Reduction by Windows Optimization.
Graph Drawing 2002: 285-294 |
| 2001 |
|---|
| 1 | EE | Bernd Becker,
Thomas Eschbach,
Rolf Drechsler,
Wolfgang Günther:
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.
DSD 2001: 54-61 |
