ASP-DAC 1995:
Makuhari,
Massa,
Chiba,
Japan
Isao Shirakawa (Ed.):
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995.
ACM 1995, ISBN 0-89791-766-9 BibTeX
@proceedings{DBLP:conf/aspdac/1995,
editor = {Isao Shirakawa},
title = {Proceedings of the 1995 Conference on Asia Pacific Design Automation,
Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995},
booktitle = {ASP-DAC},
publisher = {ACM},
year = {1995},
isbn = {0-89791-766-9},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
- Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang:
Transistor reordering rules for power reduction in CMOS gates.
Electronic Edition (link) BibTeX
- How-Rern Lin, TingTing Hwang:
Power recduction by gate sizing with path-oriented slack calculation.
Electronic Edition (link) BibTeX
- Sanjay Dhar, Dave J. Gurney:
Current and charge estimation in CMOS circuits.
Electronic Edition (link) BibTeX
- J. P. Tual, M. Thill, C. Bernard, Huy Nam Nguyen, F. Mottini, M. Moreau, P. Vallet:
Auriga2: a 4.7 million-transistor CISC microprocessor.
Electronic Edition (link) BibTeX
- Hiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito:
Automatic design for bit-serial MSPA architecture.
Electronic Edition (link) BibTeX
- Ivanil S. Bonatti, Renato J. O. Figueiredo:
Stoht: an SDL-to-hardware translator.
Electronic Edition (link) BibTeX
- Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru:
A scheduling algorithm for synthesis of bus-partitioned architectures.
Electronic Edition (link) BibTeX
- Richard K. Wallace:
Design automation 2000 (panel session): challenges for gigabit-era.
Electronic Edition (link) BibTeX
- Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran:
Reclocking for high-level synthesis.
Electronic Edition (link) BibTeX
- Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang:
Synthesis of false loop free circuits.
Electronic Edition (link) BibTeX
- Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess:
High-level synthesis scheduling and allocation using genetic algorithms.
Electronic Edition (link) BibTeX
- C.-J. Richard Shi, Janusz A. Brzozowski:
A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems.
Electronic Edition (link) BibTeX
- Eric Q. Kang, Eugene Shragowitz:
Generic fuzzy logic CAD development tool.
Electronic Edition (link) BibTeX
- Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi:
A hardware/software codesign method for pipelined instruction set processor using adaptive database.
Electronic Edition (link) BibTeX
- Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee:
EMPAR: an interactive synthesis environment for hardware emulations.
Electronic Edition (link) BibTeX
- Hae-Dong Lee, Sun-Young Hwang:
A scheduling algorithm for multiport memory minimization in datapath synthesis.
Electronic Edition (link) BibTeX
- Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha:
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping.
Electronic Edition (link) BibTeX
- J. Y. Lim, G. Kim, I.-S. O, J. H. Cho, Y. Kim, H. Y. Kim:
A CSIC implementation with POCSAG decoder and microcontroller for paging applications.
Electronic Edition (link) BibTeX
- Chunghee Kim, Hyunchul Shin, Young-Uk Yu:
Performance-driven circuit partitioning for prototyping by using multiple FPGA chips.
Electronic Edition (link) BibTeX
- Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A new system partitioning method under performance and physical constraints for multi-chip modules.
Electronic Edition (link) BibTeX
- Katsunori Tani:
A robust min-cut improvement algorithm based on dynamic look-ahead weighting.
Electronic Edition (link) BibTeX
- Sadiq M. Sait, Habib Youssef, Shahid K. Tanvir, Muhammad S. T. Benten:
Timing influenced generell-cell genetic floorplanner.
Electronic Edition (link) BibTeX
- Vivek Tiwari, Mike Tien-Chien Lee:
Power analysis of a 32-bit embedded microcontroller.
Electronic Edition (link) BibTeX
- Marco A. Escalante, Nikitas J. Dimopoulos:
Assessing the feasibility of interface designs before their implementation.
Electronic Edition (link) BibTeX
- A. Ghosh, M. Bershteyn, R. Casley, C. Chien, A. Jain, M. Lipsie, D. Tarrodaychik, O. Yamamo:
A hardware-software co-simulator for embedded system design and debugging.
Electronic Edition (link) BibTeX
- Won-Young Jung, Ghun-Up Cha, Young-Bae Kim, Jun-Ho Baek, Choon-Kyung Kim:
Integrated interconnect circuit modeling for VLSI design.
Electronic Edition (link) BibTeX
- Jong Tae Lee, Jaemin Kim, Jae Cheol Son:
Architectural simulation for a programmable DSP chip set.
Electronic Edition (link) BibTeX
- Gyeong Lyong Park, Kyung Hi Chang, Jae Seok Kim, Kyung Soo Kim:
System-level verification of CDMA modem ASIC.
Electronic Edition (link) BibTeX
- Jeongsik Yang, Chanhong Park, Beomsup Kim:
A digital audio signal processor for cellular phone application.
Electronic Edition (link) BibTeX
- Jin-Tai Yan:
Region definition and ordering assignment with the minimization of the number of switchboxes.
Electronic Edition (link) BibTeX
- Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A three-layer over-cell multi-channel routing method for a new cell model.
Electronic Edition (link) BibTeX
- Man-Fai Yu, Wayne Wei-Ming Dai:
Pin assignment and routing on a single-layer Pin Grid Array.
Electronic Edition (link) BibTeX
- Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka:
Design for testability using register-transfer level partial scan selection.
Electronic Edition (link) BibTeX
- T. Raju Damarla, Wei Su, Gerald T. Michael, Moon J. Chung, Charles E. Stroud:
A built-in self test scheme for VLSI.
Electronic Edition (link) BibTeX
- T. Bogue, Helmut Jürgensen, Michael Gössel:
BIST with negligible aliasing through random cover circuits.
Electronic Edition (link) BibTeX
- Hiroyuki Higuchi, Yusuke Matsunaga:
Implicit prime compatible generation for minimizing incompletely specified finite state machines.
Electronic Edition (link) BibTeX
- Uwe Gläser, Kwang-Ting Cheng:
Logic optimization by an improved sequential redundancy addition and removal techniques.
Electronic Edition (link) BibTeX
- Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev:
On hazard-free implementation of speed-independent circuits.
Electronic Edition (link) BibTeX
- Hiroshi Miyashita:
Extending pitchmaking algorithms to layouts with multiple grid constraints.
Electronic Edition (link) BibTeX
- Masahiro Fukui, Noriko Shinomiya, Toshiro Akino:
A new layout synthesis for leaf cell design.
Electronic Edition (link) BibTeX
- Akira Nagao, Chiyoshi Yoshioka, Takashi Kambe, Isao Shirakawa:
A layout approach to Monolithic Microwave IC.
Electronic Edition (link) BibTeX
- Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Performance driven multiple-source bus synthesis using buffer insertion.
Electronic Edition (link) BibTeX
- Christoph Scholl, Paul Molitor:
Communication based FPGA synthesis for multi-output Boolean functions.
Electronic Edition (link) BibTeX
- José M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas:
Optimum PLA folding through boolean satisfiability.
Electronic Edition (link) BibTeX
- Jung-Yong Lee, Eugene Shragowitz:
Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques.
Electronic Edition (link) BibTeX
- Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
Logic rectification and synthesis for engineering change.
Electronic Edition (link) BibTeX
- Masaharu Imai, Eugenio Villar:
Future direction of synthesizability and interoperability of HDL's: part 1.
Electronic Edition (link) BibTeX
- Bernhard M. Riess, Heiko A. Giselbrecht, Bernd Wurth:
A new K-way partitioning approach for multiple types of FPGAs.
Electronic Edition (link) BibTeX
- Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization.
Electronic Edition (link) BibTeX
- Yu-Liang Wu, Malgorzata Marek-Sadowska:
Routing on regular segmented 2-D FPGAs.
Electronic Edition (link) BibTeX
- Chip-Hong Chang, Bogdan J. Falkowski:
Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions.
Electronic Edition (link) BibTeX
- Debatosh Debnath, Tsutomu Sasao:
GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions.
Electronic Edition (link) BibTeX
- Rolf Drechsler, Bernd Becker:
Learning heuristics by genetic algorithms.
Electronic Edition (link) BibTeX
- Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga:
Optimization methods for lookup-table-based FPGAs using transduction method.
Electronic Edition (link) BibTeX
- Eugenio Villar, Masaharu Imai:
Future direction of synthesizabilty and interoperability of HDL's: part 2.
Electronic Edition (link) BibTeX
- Denis Deschacht, Christophe Dabrin:
A new and accurate interconnection delay time evaluation in a general tree-type network.
Electronic Edition (link) BibTeX
- Mikako Miyama, Goichi Yokomizo, Masato Iwabuchi, Masami Kinoshita:
An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctutation.
Electronic Edition (link) BibTeX
- Hitoshi Yoshizawa:
How sub-micron delay and timing issues will be solved?
Electronic Edition (link) BibTeX
- Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
A model-adaptable MOSFET parameter extraction system.
Electronic Edition (link) BibTeX
- Per Lindgren:
Improved computational methods and lazy evaluation of the Ordered Ternary Decision Diagram.
Electronic Edition (link) BibTeX
- Radomir S. Stankovic:
Some remarks about spectral transform interpretation of MTBDDs and EVBDDs.
Electronic Edition (link) BibTeX
- Shinya Ishihara, Shin-ichi Minato:
Manipulation of regular expressions under length constraints using zero-suppressed-BDDs.
Electronic Edition (link) BibTeX
- Jason Cong, Dongmin Xu:
Exploitation signal flow and logic dependency in standard cell placement.
Electronic Edition (link) BibTeX
- Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru:
A new performance driven placement method with the Elmore delay model for row based VLSIs.
Electronic Edition (link) BibTeX
- Morteza Saheb Zamani, Graham R. Hellestrand:
A neural network approach to the placement problem.
Electronic Edition (link) BibTeX
- T. Aoki, Masami Murakata, Takashi Mitsuhashi, Nobuyuki Goto:
Fanout-tree restructuring algorithm for post-placement timing optimization.
Electronic Edition (link) BibTeX
- Hiroshi Uno, Toru Chiba, Keiji Kumatani, Isao Shirakawa:
Synthesis and simulation of digital demodulator for infrared data communication.
Electronic Edition (link) BibTeX
- Hilary J. Kahn:
EDIF version 350/400 and information modeling.
Electronic Edition (link) BibTeX
- Keisuke Okada, Shun Morikawa, Isao Shirakawa, Sumitaka Takeuchi:
A design of high-performance multiplier for digital video transmission.
Electronic Edition (link) BibTeX
- Kazuyuki Wada, Shigetaka Takagi, Zdzislaw Czarnul, Nobuo Fujii:
Design automation for integrated continuous-time filters using integrators.
Electronic Edition (link) BibTeX
- Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao:
A hardware-oriented design for weighted median filters.
Electronic Edition (link) BibTeX
- Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Techniques for low power realization for FIR filters.
Electronic Edition (link) BibTeX
- Noriya Kobayashi, Sharad Malik:
Delay abstraction in combinational logic circuits.
Electronic Edition (link) BibTeX
- Janett Mohnke, Paul Molitor, Sharad Malik:
Limits of using signatures for permutation independent Boolean comparison.
Electronic Edition (link) BibTeX
- Takashi Aoki, Tomoji Toriyama, Kenji Ishikawa, Kennosuke Fukami:
A tool for measuring quality of test pattern for LSIs' functional design.
Electronic Edition (link) BibTeX
- Atsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, Masatoshi Sekine:
Search space reduction in high level synthesis by use of an initial circuit.
Electronic Edition (link) BibTeX
- Reiner W. Hartenstein, Rainer Kress:
A datapath synthesis system for the reconfigurable datapath architecture.
Electronic Edition (link) BibTeX
- Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
Synthesis-for-testability using transformations.
Electronic Edition (link) BibTeX
- Kinya Tabuchi:
Electronic data book: current status of standard representation and future perspective.
Electronic Edition (link) BibTeX
Copyright © Sat May 16 22:58:43 2009
by Michael Ley (ley@uni-trier.de)