| 2007 |
|---|
| 27 | EE | Marcel Baunach,
Reiner Kolla,
Clemens Muhlberger:
A Method for Self-Organizing Communication in WSN Based Localization Systems: HashSlot.
LCN 2007: 825-832 |
| 26 | EE | Marcel Baunach,
Reiner Kolla,
Clemens Muhlberger:
Beyond Theory: Development of a Real World Localization Application as Low Power WSN.
LCN 2007: 872-884 |
| 2003 |
|---|
| 25 | EE | Frank Wolz,
Reiner Kolla:
Disproving the Perfect-Rate Property of Data-Flow Graphs Unfolded by the Least Common Multiple of the Number of Loop Registers.
IEEE Trans. Computers 52(5): 688 (2003) |
| 2002 |
|---|
| 24 | EE | Frank Wolz,
Reiner Kolla:
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures.
FPL 2002: 997-1006 |
| 2001 |
|---|
| 23 | EE | Frank Wolz,
Reiner Kolla:
Bubble Partitioning for LUT-Based Sequential Circuits.
FPL 2001: 336-345 |
| 2000 |
|---|
| 22 | EE | Frank Wolz,
Reiner Kolla:
A New Floorplanning Method for FPGA Architectural Research.
FPL 2000: 432-442 |
| 21 | EE | Reiner Kolla:
Technology Binding.
Informatik Spektrum 23(3): 212-215 (2000) |
| 1999 |
|---|
| 20 | | Reiner Kolla,
A. Vodopivec,
Jürgen Wolff von Gudenberg:
Splitting Double Precision FPUs for Single Precision Interval Arithmetic.
ARCS Workshops 1999: 5-16 |
| 19 | EE | Winfried Nöth,
Reiner Kolla:
Spanning Tree-based State Encoding for Low Power Dissipation.
DATE 1999: 168-174 |
| 1998 |
|---|
| 18 | EE | Uwe Hinsberger,
Reiner Kolla:
Boolean Matching for Large Libraries.
DAC 1998: 206-211 |
| 17 | | Reiner Kolla,
Oliver Springauf:
PACE: Processor Architectures for Circuit Emulation.
IPPS/SPDP Workshops 1998: 105-110 |
| 1997 |
|---|
| 16 | | Uwe Hinsberger,
Reiner Kolla,
Markus Wild:
A parallel hybrid approach to hard optimization problems.
ARCS 1997: 201-210 |
| 15 | EE | Winfried Nöth,
Reiner Kolla:
Node normalization and decomposition in low power technology mapping.
ISLPED 1997: 275-280 |
| 1996 |
|---|
| 14 | EE | Winfried Nöth,
Uwe Hinsberger,
Reiner Kolla:
TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping.
Great Lakes Symposium on VLSI 1996: 188-193 |
| 1995 |
|---|
| 13 | EE | Uwe Hinsberger,
Reiner Kolla:
Optimal technology mapping for single output cells.
Great Lakes Symposium on VLSI 1995: 14- |
| 1992 |
|---|
| 12 | EE | Uwe Hinsberger,
Reiner Kolla:
A cell-based approach to performance optimization of fanout-free circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1317-1322 (1992) |
| 1991 |
|---|
| 11 | | Reiner Kolla,
Bernd Serf:
The Virtual Feedback Problem in Hierarchical Representations of Combinational Circuits.
Acta Inf. 28(5): 463-476 (1991) |
| 1990 |
|---|
| 10 | EE | Bernd Becker,
Thomas Burch,
Günter Hotz,
D. Kiel,
Reiner Kolla,
Paul Molitor,
Hans-Georg Osthof,
Gisela Pitsch,
Uwe Sparmann:
A graphical system for hierarchical specifications and checkups of VLSI circuits.
EURO-DAC 1990: 174-179 |
| 9 | EE | Uwe Hinsberger,
Reiner Kolla:
Cell based performance optimization of combinational circuits.
EURO-DAC 1990: 594-599 |
| 8 | EE | Reiner Kolla:
A dynamic programming approach to the power supply net sizing problem.
EURO-DAC 1990: 600-604 |
| 7 | | Reiner Kolla:
Minimal Area Sizing of Power Supply Nets in VLSI Circuits.
Elektronische Informationsverarbeitung und Kybernetik 26(11/12): 585-605 (1990) |
| 1988 |
|---|
| 6 | | Bernd Becker,
Reiner Kolla:
On the Construction of Optimal Time Adders (Extended Abstract).
STACS 1988: 18-28 |
| 1987 |
|---|
| 5 | EE | Bernd Becker,
Günter Hotz,
Reiner Kolla,
Paul Molitor,
Hans-Georg Osthof:
Hierarchical Design Based on a Calculus of Nets.
DAC 1987: 649-653 |
| 1986 |
|---|
| 4 | | Günter Hotz,
Reiner Kolla,
Paul Molitor:
On Network Algebras and Recursive Equations.
Graph-Grammars and Their Application to Computer Science 1986: 250-261 |
| 3 | | Günter Hotz,
Bernd Becker,
Reiner Kolla,
Paul Molitor:
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I.
Inform., Forsch. Entwickl. 1(1): 38-47 (1986) |
| 2 | | Günter Hotz,
Bernd Becker,
Reiner Kolla,
Paul Molitor:
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II.
Inform., Forsch. Entwickl. 1(2): 72-82 (1986) |
| 1983 |
|---|
| 1 | | Reiner Kolla:
Where-Oblivious is not Sufficient.
Inf. Process. Lett. 17(5): 263-268 (1983) |
