ISVLSI 2008:
Montpellier,
France
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France.
IEEE Computer Society 2008 BibTeX
Keynotes
Design of Arithmetic VLSI Circuits
Architecture & SoC Design
Emerging Technologies
Heterogeneous System Design
- Fahd Ben Abdeljelil, Benjamin Nicolle, William Tatinian, Lorenzo Carpineto, Jean Oudinot, Gilles Jacquemod:
Application of Bottom-Up Methodology to RTW VCO.
46-50
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- Olivier Leman, Laurent Latorre, Frédérick Mailly, Pascal Nouet:
A Closed-Loop Architecture with Digital Output for Convective Accelerometers.
51-56
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- Boris Alandry, Norbert Dumas, Laurent Latorre, Frédérick Mailly, Pascal Nouet:
A CMOS Multi-sensor System for 3D Orientation Determination.
57-62
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Low Power Design I
Multiprocessor SoC
- Ralf Laue, H. Gregor Molter, Felix Rieder, Sorin A. Huss, Kartik Saxena:
A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications.
87-92
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- Issam Maalej, Guy Gogniat, Jean Luc Philippe, Mohamed Abid:
System Level Design Space Exploration for Multiprocessor System on Chip.
93-98
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- Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar:
A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures.
99-104
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- Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert:
MPI-Based Adaptive Task Migration Support on the HS-Scale System.
105-110
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Low Power Design II
- Bahar Jalali Farahani, Anand Meruva:
Low Power High Performance Digitally Assisted Pipelined ADC.
111-116
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- Rong Ji, Liang Chen, Gang Luo, Xianjun Zeng, Junfeng Zhang, Yingjie Feng:
A Novel Low-Power Clock Skew Compensation Circuit.
117-121
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- Yngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet:
High Speed Ultra Low Voltage CMOS inverter.
122-127
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- Lingamneni Avinash, Kirthi Krishna Muntimadugu, M. B. Srinivas:
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection.
128-133
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System Level Testing
High Performance Circuits
Mixed Signal Design
Nanoscale Circuits
Telecom & Multimedia Architecture Design and Modeling
Physical Design
Test & Verification
- Selina Sha, Bruce Swanson:
A Real Case of Significant Scan Test Cost Reduction.
239-244
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- Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan:
A Network Based Functional Verification Method of IEEE 1394a PHY Core.
245-250
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- Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan:
Cohesive Coverage Management for Simulation and Formal Property Verification.
251-256
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- Ilia Polian, Sudhakar M. Reddy, Bernd Becker:
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.
257-262
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Models for low Power Design
Dynamic Reconfiguration Management Techniques
- Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto:
Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture.
286-291
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- Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Tomasz Surmacz:
SeReCon: A Secure Dynamic Partial Reconfiguration Controller.
292-297
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- Maik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke:
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs.
298-303
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- Katarina Paulsson, Ulrich Viereck, Michael Hübner, Jürgen Becker:
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs.
304-309
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Hot Topic :
Variability-Insensitive Design Techniques
- Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert:
Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects.
310-315
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- Bettina Rebaud, Marc Belleville, Christian Bernard, Zequin Wu, Michel Robert, Philippe Maurine, Nadine Azémard:
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier.
316-321
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- N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung:
Characterisation of FPGA Clock Variability.
322-328
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- Venkataraman Mahalingam, Nagarajan Ranganathan:
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing.
329-334
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Network On Chip
VLSI Circuits
Hot Topic :
Temperature-aware Design
- Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami:
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection.
363-368
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- Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations.
369-374
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- Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory.
375-380
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Reconfigurable-based Circuits & Methods
System Level Design & Tools
- David Andreu, Guillaume Souquet, Thierry Gil:
Petri Net Based Rapid Prototyping of Digital Complex System.
405-410
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- Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler:
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability.
411-416
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- Fabrizio Ferrandi, Pier Luca Lanzi, Daniele Loiacono, Christian Pilato, Donatella Sciuto:
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis.
417-422
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- Hariharan Sankaran, Srinivas Katkoori:
Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis.
423-428
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Posters 1
- Padnamabhan Balasubramanian, D. A. Edwards:
Efficient Realization of Strongly Indicating Function Blocks.
429-432
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- Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol:
Virtual Point-to-Point Links in Packet-Switched NoCs.
433-436
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- Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled:
Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip.
437-440
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- Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
A Web Server Based Edge Detector Implementation in FPGA.
441-446
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- Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara:
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways.
447-450
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- Serge Burckel, Emeric Gioan:
In Situ Design of Register Operations.
451-454
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- Hongbin Sun, Nanning Zheng, Chenyang Ge, Dong Wang, Pengju Ren:
An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design.
455-458
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- Rupsa Chakraborty, Dipanwita Roy Chowdhury:
Raising the Level of Abstraction for the Timing Verification of System-on-Chips.
459-462
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- Hugo Lebreton, Pacal Vivet:
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture.
463-466
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- Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi:
Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement.
467-470
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- Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani:
Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions.
471-474
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Posters 2
- Guilherme Guindani, Cezar Reinbrecht, T. Raupp, Ney Calazans, Fernando Gehm Moraes:
NoC Power Estimation at the RTL Abstraction Level.
475-478
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- Ahmed Jedidi, Badreddine Rejeb, Mohamed Abid:
Design of Fractal Image Compression on SOC.
479-482
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- Jin-Hua Hong, Wen-Jie Li:
A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier.
483-486
Electronic Edition (link) BibTeX
- Fabien Soulier, Jean-Baptiste Lerat, Lionel Gouyet, Serge Bernard, Guy Cathébras:
A Neural Stimulator Output Stage for Dodecapolar Electrodes.
487-490
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- Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Fernando Moraes, Manfred Glesner:
Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects.
491-494
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- Yosi Ben-Asher, Eddie Shochat:
Finding the Best Compromise in Compiling Compound Loops to Verilog.
495-498
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- Xun Zhang, Hassan Rabah, Serge Weber:
An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip.
499-502
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- Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang:
An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES.
503-506
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- Mehrdad Najibi, Hossein Pedram:
Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading.
507-510
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- Daisaku Seto, Minoru Watanabe:
A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory.
511-514
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Copyright © Sat May 16 23:26:33 2009
by Michael Ley (ley@uni-trier.de)