11. DDECS 2008:
Bratislava,
Slovakia
Bernd Straube, Milos Drutarovský, Michel Renovell, Peter Gramata, Mária Fischerová (Eds.):
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008.
IEEE Computer Society 2008, ISBN 978-1-4244-2276-0 BibTeX
Invited Presentations
Poster Session I
- Dimitar P. Dimitrov:
Deep-Submicron MOS Transistor Matching: A Case Study.
4-7
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- Håvard Pedersen Alstad, Snorre Aunet:
Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology.
8-11
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- Håvard Pedersen Alstad, Snorre Aunet:
Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation.
12-13
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- Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures.
14-17
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- Vladimir Havel, Karel K. Vlcek:
Computation of a nonlinear squashing function in digital neural networks.
18-21
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- Stanislaw Deniziak, Mariusz Wisniewski:
An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs.
22-25
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- Libor Majer, Viera Stopjaková:
Portable Measurement Equipment for Continuous Biomedical Monitoring using Microelectrodes.
26-29
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- Konstantin V. Shinkarenko, Karel K. Vlcek:
Design of Erasure Codes for Digital Multimedia Transmitting.
30-33
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- Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.
34-37
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Process Variations Aware Design
Physical Design
ATPG and Fault Tolerance
SoC and NoC Design
Digital Design Methods
Poster Session II
- Grzegorz Janczyk, Tomasz Bieniek:
The HDL and FE Thermal Modeling of Heterogeneous Systems.
128-131
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- Zoran Stamenkovic, Goran Panic, Günter Schoof:
A System-On-Chip for Wireless Body Area Sensor Network Node.
132-135
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- Frantisek Reznicek:
Mixed-Signal DFT for fully testable ASIC.
136-139
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- Karel Dudacek:
On Minimizing RTOS Aperiodic Tasks Server Energy Consumption.
140-143
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- Miroslav Manik, Elena Gramatová:
Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor Systems.
144-145
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- Virgil E. Petcu, Alexandru Amaricai, Mircea Vladutiu:
A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units.
146-149
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- Marek Miskowicz:
Design of Time-to-Digital Converter Output Interface.
150-153
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- Thilo Pionteck, Carsten Albrecht, Roman Koch, Torben Brix, Erik Maehle:
Design and Simulation of Runtime Reconfigurable Systems.
154-157
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ASIC and FPGA Design
Student Papers
Design Verifications
- José Augusto Miranda Nacif, Thiago Silva, Andréa Iabrudi Tavares, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.:
Efficient Allocation of Verification Resources using Revision History Information.
190-194
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- Christian Haufe, Frank Rogin:
Ad-Hoc Translations to Close Verilog Semantics Gap.
195-200
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- Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee:
Code Coverage Analysis using High-Level Decision Diagrams.
201-206
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- Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker:
Probabilistic Model Checking and Reliability of Results.
207-212
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Industrial Papers I
Industrial Papers II
Poster Session III
- Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec:
Interconnect Faults Identification and Localization Using Modified Ring LFSRs.
247-250
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- Dimitrios K. Konstantinou, Michael G. Dimopoulos, Dimitris K. Papakostas, Alkis A. Hatzopoulos, Alexios Spyronasios:
Testing an Emergency Luminaire Circuit Using a Fault Dictionary Approach.
251-254
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- Lukás Starecek, Lukás Sekanina, Zdenek Kotásek:
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration.
255-268
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- Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková:
Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology.
259-262
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- Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen:
Diagnosis of Realistic Defects Based on the X-Fault Model.
263-266
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- Werner Friesenbichler, Thomas Panhofer, Martin Delvai:
Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits.
267-270
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- Eero Ivask, Jaan Raik, Raimund Ubar:
Web-Based Framework for Parallel Distributed Test.
271-274
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- Artur Jutman, Anton Tsertov, Raimund Ubar:
Calculation of LFSR Seed and Polynomial Pair for BIST Applications.
275-278
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- Lukas Chruszczyk, Jerzy Rutkowski:
Excitation optimization in fault diagnosis of analog electronic circuits.
279-282
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- Ondrej Subrt, Petr Struhovský, Pravoslav Martínek, Jirí Hospodka:
Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform.
283-286
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Analog Test
BIST and Mems Test
SoC and Memory Test
- Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi:
SoC Symbolic Simulation: a case study on delay fault testing.
320-325
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- Michael Higgins, Ciaran MacNamee, Brendan Mullane:
SoCECT: System on Chip Embedded Core Test.
326-331
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- Ireneusz Mrozek, Vyacheslav Yarmolik:
Optimal Backgrounds Selection for Multi Run Memory Testing.
332-338
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- Wilson J. Perez, Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda:
Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs.
339-344
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Copyright © Sat May 16 23:06:18 2009
by Michael Ley (ley@uni-trier.de)
