VLSI 2003:
Las Vegas,
Nevada,
USA
Hamid R. Arabnia, Laurence Tianruo Yang (Eds.):
Proceedings of the International Conference on VLSI, VLSI '03, June 23 - 26, 2003, Las Vegas, Nevada, USA.
CSREA Press 2003, ISBN 1-932415-10-6 BibTeX
@proceedings{DBLP:conf/vlsi/2003,
editor = {Hamid R. Arabnia and
Laurence Tianruo Yang},
title = {Proceedings of the International Conference on VLSI, VLSI '03,
June 23 - 26, 2003, Las Vegas, Nevada, USA},
booktitle = {VLSI},
publisher = {CSREA Press},
year = {2003},
isbn = {1-932415-10-6},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Digital Signal Processing
Reconfigurable Computing
Fault Tolerance
Low Power Design
Noise Reduction and Crosstalk
Circuits and Systems
- Manfred Schimmler, Bertil Schmidt, Hans-Werner Lang, Sven Heithecker:
An Area-Efficient Bit-Serial Integer Multiplier.
131-137 BibTeX
- Ali Telli, Simsek Demir, Murat Askar:
Planar Spiral Inductor Modeling for RFIC Design.
138-142 BibTeX
- Scott C. Smith:
Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy.
143-149 BibTeX
- Volnei A. Pedroni:
High-Resolution WTA-MAX Circuit for Large Networks.
150-154 BibTeX
- Adnan M. Lokhandwala, Sudip K. Mazumder:
A Novel Smart Power ASIC (SPIC) for Integrated Control of Cascaded Power Converters.
155-161 BibTeX
- Youngsoo Kim, Janghong Yoon, Sungok Kim:
An Improved Circuit Design for Parallel Sequence Generation.
162-165 BibTeX
- Khia-Ho Chang, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File.
166-172 BibTeX
- Yil Suk Yang, Jongdae Kim, Tae Moon Roh, Dae Wood Lee, Sung-Ku Kwon, Il Yong Park, Byoung Gon Yu:
Level Shifter Circuit Having Dual Outputs for FPD Gate Driver.
173-177 BibTeX
- Satish K. Bandapati, Scott C. Smith:
Design and Characterization of NULL Convention Arithmetic Logic Units.
178-184 BibTeX
- Kang Hyeon Rhee:
A Study on the 8bit Pipeline RISC Processor.
185-189 BibTeX
- Evandro de Araújo Jardini, Dilvan de Abreu Moreira:
Multithreaded parallel VLSI Leaf Cell Generator Using Agents 2.
190-196 BibTeX
Quantum Computing
Testing and Verification
Devices and Circuits
- Yiming Li, Shao-Ming Yu, Hsiao-Mei Lu:
Intelligent Device Parameter Extraction for Nanoscale MOSFETs Era.
233-239 BibTeX
- J. K. Kim, S. H. Won, Ki-Seok Chung, H. D. Cho, T. W. Kang, T. S. Nam, C. S. Kang, C. H. Yi, D. S. Kim:
Properties of A1/BaTa2O6/GaN MIS Structure.
240-243 BibTeX
- Shih-Ching Lo, Jyun-Hwei Tsai, Jer-Ming Hsu, Yiming Li:
Quantum Mechanical Gate Current Simulation in MOSFETs with Ultrathin Oxides.
244-250 BibTeX
- Jam Wem Lee, Yiming Li, Howard Tang:
Silicide Optimization for Electrostatic Discharge Protection Devices in Sub-100 nm CMOS Circuit Design.
251-260 BibTeX
High-Level Design
Complexity Issues
- Manfred Schimmler, Viktor Bunimov:
A Simple Circuit to Reduce the Search Range for Large Prime Numbers.
285-291 BibTeX
- Rita M. Hare, Bryant A. Julstrom:
A Genetic Algorithm for Restricted Cases of the Rectilinear Steiner Problem with Obstacles.
292-297 BibTeX
- Todd W. Neller, David C. Hettlinger:
Learning Annealing Schedules for Channel Routing.
298-302 BibTeX
- Andris Ambainis, Uldis Barbans, Agnese Belousova, Aleksandrs Belovs, Ilze Dzelme, Girts Folkmanis, Rusins Freivalds, Peteris Ledins, Rihards Opmanis, Agnis Skuskovniks:
Size of Quantum Versus Deterministic Finite Automata.
303-308 BibTeX
- Lelde Lace, Rusins Freivalds:
Lower Bounds for Query Complexity of Some Graph Problems.
309-316 BibTeX
Security Application
Applications,
Algorithms + Novel Designs
- Mitra Mirhassani, Majid Ahmadi, William C. Miller:
A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays.
339-344 BibTeX
- Jaime Ramírez-Angulo, Chandrika Durbha, Gladys Omayra Ducoudray, Ramón González Carvajal:
Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong Inversion.
345-350 BibTeX
- Bhupen P. Zaveri:
Phase Coincidence Technique for Frequency Difference Measurement.
351-355 BibTeX
- Jae-Young Yi, Yong-Hui Lee, Cheon-Hee Yi:
PEDE (Plasma Edge Damage Effect) Curing by Various Heat Treatment.
356-360 BibTeX
- Vishal Verma, Himanshu Thapliyal:
A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics.
361-365 BibTeX
- YunKyung Lee, YoungSu Park:
High Speed, Small Area AES Block Cipher Coprocessor Design for USIM Card.
366-372 BibTeX
Late Papers and Post-Conference Papers
Copyright © Sat May 16 23:46:40 2009
by Michael Ley (ley@uni-trier.de)
