25. ISMVL 1995: Bloomington, Indiana, USA

25th IEEE International Symposium on Multiple-Valued Logic (ISMVL 1995), May 23 - 25, 1995, Bloomington, Indiana, USA, Proceedings. IEEE Computer Society, 1995, online publication: http: //computer.org/proceedings/ismvl/7118/7118toc.htm

VLSI

Jens Kargaard Madsen, Stephen I. Long:
A High-Speed Interconnect Network Using Ternary Logic. 2-7
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S. Sakurai, Takafumi Aoki, Tatsuo Higuchi:
Wire-Free Computing Circuits Using Optical Wave-Casting. 8-13
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Y. Ohi, Takafumi Aoki, Tatsuo Higuchi:
Redundant Complex Number Systems. 14-19
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M. Ryu, Michitaka Kameyama:
Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. 20-
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Logic Design I

Tsutomu Sasao, Jon T. Butler:
Planar Multiple-Valued Decision Diagrams. 28-35
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Zeljko Zilic, Zvonko G. Vranesic:
Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. 36-43
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R. Oenning, Claudio Moraga:
Properties of the Zhang-Watari Transform. 44-
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Circuit Design I

K. Wayne Current:
Memory Circuits for Multiple-Valued Logic Voltage Signals. 52-57
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Keivan Navi, Daniel Etiemble:
From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators. 58-63
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Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. 64-
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Algebra I

J. Beckman, T. C. Wesselkamper:
The Radii of Sheffer Functions Over E(3). 72-77
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Alioune Ngom, Corina Reischer, Ivan Stojmenovic:
Classification of Functions and Enumeration of Bases of Set Logic under Boolean Compositions. 78-85
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B. A. Romov:
Completeness Theory for Vector Partial Multiple-Valued Logic Functions. 86-
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Device-Based Circuit and Testing I

Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama:
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. 92-97
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Rolf Drechsler, Rolf Krieger, Bernd Becker:
Random Pattern Fault Simulation in Multi-Valued Circuits. 98-103
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Elena Dubrova, Dilian Gurov, Jon C. Muzio:
The Evaluation of Full Sensitivity for Test Generation in MVL Circuits. 104-
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Logic I

Zuoquan Lin:
Paraconsistent Circumscription: First-Order Case. 112-116
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Bogdan J. Falkowski, Susanto Rahardja:
Novel Quantized Transform for Ternary Systems. 117-122
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Seiki Akama, Y. Nakayama:
A Three-Valued Semantics for Discourse Representations. 123-
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Invited Address

Takao Waho:
Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits. 130-
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Fuzzy Logic

Helmut Thiele:
On the Mutual Definability of Fuzzy Tolerance Relations and Fuzzy Tolerance Coverings. 140-145
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N. Schmechel:
On Lattice-Isomorphism Between Fuzzy Equivalence Relations and Fuzzy Partitions. 146-151
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Liusheng Liu, Zhijian Li, Bingxue Shi:
Segment Matrix Vector Quantization and Fuzzy Logic for Isolated-Word Speech Recognition. 152-
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Logic Design II

Bogdan J. Falkowski, Susanto Rahardja:
Efficient Algorithm for the Generation of Fixed Polarity Quaternary Reed-Muller Expansions. 158-163
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Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Factorization of Multi-Valued Logic Functions. 164-169
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Yutaka Hata, Naotake Kamiura, Kazuharu Yamato:
On Input Permutation Technique for Multiple-Valued Logic Synthesis. 170-
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Device-Based Circuit and Testing II

Shoujue Wang, Xunwei Wu, Hongjuan Feng:
The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. 178-181
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Hao Tang, Hung Chang Lin:
A Fuzzy Membership Function Circuit Using Hysteretic Resonant Tunneling Diodes. 182-186
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Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang:
On Designing of 4-Valued Memory with Double-Gate TFT. 187-
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Algebra II

Grant Pogosyan, Akihiro Nozaki:
Join-Irreducible Clones of Multiple-Valued Logic Algebra. 194-199
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Hajime Machida:
Finitary Approximations and Metric Structure of the Space of Clones. 200-205
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Wendy MacCaull:
Finite Algebraic Models for Residuated Logic. 206-
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Circuit Design II

A. K. Jain, Mostafa H. Abd-El-Barr, R. J. Bolton:
Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm. 216-221
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Xunwei Wu, Xiexiong Chen, Jizhong Shen:
Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits. 222-227
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R. Murakami, Yoshiteru Ohkura, Ryosaku Shimada:
2^k-ary Cyclic AN Codes for Burst Error Correction. 228-
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Logic II

Noboru Takagi, Hiroaki Kikuchi, Kyoichi Nakashima, Masao Mukaidono:
A Characterization of Kleenean Functions. 236-241
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Hiroaki Kikuchi, Noboru Takagi, Shohachiro Nakanishi, Masao Mukaidono:
Uniqueness of Partially Specified Multiple-Valued Kleenean Function. 242-247
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Zuoquan Lin, Wei Li:
On Logic of Paradox. 248-
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Invited Address

Tadeusz Luba:
Decomposition of Multiple-Valued Functions. 256-
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Artificial Intelligence

T. C. Wesselkamper, J. Danowitz:
Some New Results for Multiple-Valued Genetic Algorithms. 264-
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Zheng Tang, Okihiko Ishizuka, Koichi Tanno:
Learning Multiple-Valued Logic Networks Based on Back Propagation. 270-275
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Seiki Akama:
Three-Valued Constructive Logic and Logic Programs. 276-
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Logic Design III

Radomir S. Stankovic:
Functional Decision Diagrams for Multiple-Valued Functions. 284-189
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Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato:
Multiple-Valued Logic Design Using Multiple-Valued EXOR. 290-295
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