ISCAS 1999:
Orlando,
Florida,
USA - Volume 6
International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA.
IEEE 1999, ISBN 0-7803-5471-0 BibTeX
- Axel Wenzler, Ernst Lücker:
Analysis of the periodic steady-state in nonlinear circuits using an adaptive function base.
1-4
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- D. M. W. Leenaerts:
Symbolic analysis of large signals in nonlinear systems.
5-8
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- C. M. Arturi, A. Gandelli, S. Leva, S. Marchi, A. P. Morando:
Multiresolution analysis of time-variant electrical networks.
9-13
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- Takashi Hisakado, Kohshi Okumura:
Steady states prediction in nonlinear circuit by wavelet transform.
14-17
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- P. Eriksson, Hannu Tenhunen:
A model for predicting sampler RF bandwidth and conversion loss.
18-21
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- Dario D'Amore, Paolo Maffezzoni:
A new diode model formulation for electro-thermal analysis.
22-25
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- C. S. Petrie, J. Alvin Connelly:
The sampling of noise for random number generation.
26-29
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- Kam-Weng Tam, P. Viror, J. C. Freire, Rui Paulo Martins:
New microwave bandstop filter using lumped and transversal network.
30-32
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- A. Kamo, T. Watanabe, H. Asai:
Expanded GMC for transient analysis of transmission line networks.
33-36
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- D. B. Carvalho, Sidnei Noceti Filho, Rui Seara:
Design of phase equalizers via symmetry of the impulse response.
37-40
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- Corneliu Rusu, Pauli Kuosmanen:
Logarithmic sampling of gain and phase approximation.
41-44
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- Kisuk Yoo, Sanggee Kang, Jae-Ick Choi, Jong-Suk Chae:
Adaptive feed-forward linear power amplifier (LPA) for the IMT-2000 frequency band.
45-48
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- David Báez-López, E. Jimenez-Lopez:
A modified inverse-Chebyshev filter with an all positive elements ladder passive realization.
49-52
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- L. A. Carastro, R. Poddar, E. Moon, Martin A. Brooke, Nan M. Jokerst:
Passive device modeling methodology using nonlinear optimization.
53-56
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- Bor-Ren Lin, Hsin-Hung Lu:
Multilevel PWM for single-phase power factor pre-regulator.
57-60
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- Michiel H. L. Kouwenhoven, J. Mulder, Wouter A. Serdijn, Arthur H. M. van Roermund:
Analysis of noise in higher-order translinear filters.
61-64
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- G. Efthivoulidis, Yannis P. Tsividis:
Signal analysis of externally linear filters.
65-68
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- F. C. M. Kuijstermans, F. M. Diepstraten, Wouter A. Serdijn, P. van der Kloet, Arie van Staveren, Arthur H. M. van Roermund:
The linear time-varying approach applied to a first-order dynamic translinear filter.
69-72
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- M. Keramat:
Theoretical bases of convolution technique in gradient estimation of average quality index of electronic circuits.
73-76
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- Bor-Ren Lin, Yuen-Chou Hsieh:
High power factor of metal halide lamp with dimming control.
77-80
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- M. Yamauchi, T. Watanabe:
A heuristic algorithm SDS for scheduling with timed Petri nets.
81-84
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- J. Martínez-Castillo, J. Silva-Martinez:
Transimpedance amplifiers for optical fiber systems based on common-base transistors.
85-88
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- Chang-Hyeon Lee, K. McCellan, John Choma Jr.:
Supply noise insensitive bandgap regulator using capacitive charge pump DC-DC converter.
89-92
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- Laleh Behjat, Anthony Vannelli:
VLSI concentric partitioning using interior point quadratic programming.
93-96
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- A. Harb, Mohamad Sawan:
New low-power low-voltage high-CMRR CMOS instrumentation amplifier.
97-100
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- P. A. Ramamoorthy:
Nonlinear signal processor design: a building block approach.
101-104
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- R. J. Pieper, S. Michael:
Circuit modeling to predict the performance of force-cooled cold plate structures.
105-108
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- M. D. Bagewadi, B. G. Fernandes, R. V. S. Subrahmanyam:
A novel QRDCL circuit for zero voltage switched inverter.
109-112
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- D. L. Youngblood:
Multi-mode impedance synthesis for subscriber line applications.
113-116
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- Guo-Hui Lin, Guoliang Xue:
Balancing Steiner minimum trees and shortest-path trees in the rectilinear plane.
117-120
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- E. Miuno, T. Abaashi, T. Watanabe:
Extracting nonplanar connections in a terminal-vertex graph.
121-124
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- Guo-Hui Lin, A. P. Thurber, Guoliang Xue:
The 1-Steiner tree problem in lambda-3 geometry plane.
125-128
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- K. Tsuji:
Structural properties for transformation of extended marked graphs.
129-132
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- R. Vargas Bernal, A. Samtiento Reyes:
A topology-based method for identifying flip-flop graphs in BJT circuits.
133-136
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- Jun Inagaki, Miki Haseyama, Hideo Kitajima:
A genetic algorithm for determining multiple routes and its applications.
137-140
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- J. Scanlon, N. Deo:
Graph-theoretic algorithms for image segmentation.
141-144
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- Gregory Tumbush, Dinesh Bhatia:
Clustering to improve bi-partition quality and run time.
145-148
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- Chen Liu, Mingde Dai, Xin-Yu Wu, Wai-Kai Chen:
A new algorithm for computing the overall network reliability.
149-152
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- Hiroshi Tamura, Masakazu Sengoku, Keisuke Nakano, Shoji Shinoda:
Graph theoretic or computational geometric research of cellular mobile communications.
153-156
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- Hongfang Liu, D. Frank Hsu, S. Horiguchi:
Generalized shuffle-exchange digraphs: Hamiltonian properties.
157-160
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- Krishnaiyan Thulasiraman, Anindya Das, Kaiyuan Huang, Vinod K. Agarwal:
Correct diagnosis of almost all faulty units in a multiprocessor system.
161-164
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- T. Yamada, S. Imai, S. Ueno:
On VLSI decompositions for deBruijn graphs.
165-169
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- Wai-Kei Mak, D. F. Wong:
A fast hypergraph minimum cut algorithm.
170-173
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- Kengo R. Azegami, Atsushi Takahashi, Y. Kajitan:
Enumerating the min-cuts for applications to graph extraction under size constraints.
174-177
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- M. Sarrafzadeh, T. Takahashi:
A fast algorithm for routability testing.
178-181
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- Guoliang Xue, Guo-Hui Lin, Ding-Zhu Du:
Grade of service Euclidean Steiner minimum trees.
182-185
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- John P. Fishburn:
Optimization-based calibration of a static timing analyzer to path delay measurements.
186-189
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- Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Signal waveform characterization in RLC trees.
190-193
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- Jinghong Chen, Sung-Mo Kang:
A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits.
194-197
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- Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos:
An analytical, transistor-level energy model for SRAM-based caches.
198-201
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- S. Pavan, Yannis P. Tsividis, K. Nagaraj:
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes.
202-205
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- E. Gondro, P. Klein, F. Schuler:
An analytical source-and-drain series resistance model of quarter micron MOSFETs and its influence on circuit simulation.
206-209
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- Sang Won Song, M. Ismail, Gyu Moon, Dong Yong Kim:
Accurate modeling of simultaneous switching noise in low voltage digital VLSI.
210-213
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- Yi-Kan Cheng, Sung-Mo Kang:
Temperature-driven power and timing analysis for CMOS ULSI circuits.
214-217
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- Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez:
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes.
218-221
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- Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti:
Statistical modeling of MOS transistor mismatch based on the parameters' autocorrelation function.
222-225
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- J. H. Wang:
Event-overlapping processing in current waveform simulation.
226-229
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- T. Myono, E. Nishibe, S. Kikuchi, K. Iwatsu, T. Suzuki, Y. Sasaki, K. Itoh, H. Kobayashi:
Modeling and parameter extraction technique for high-voltage MOS device.
230-233
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- Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioannis Tsoukalas, Odysseas G. Koufopavlou:
CMOS gate modeling based on equivalent inverter.
234-237
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- R. Lowther:
Compact modeling of interconnect and substrate coupling at GHz frequencies.
238-241
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- Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar:
Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques.
242-245
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- Zhong-Fang Jin, J.-J. Laurin, Yvon Savaria, P. Garon:
A new approach to analyze interconnect delays in RC wire models.
246-249
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- Ninglong Lu, Ibrahim N. Hajj:
A reduced-order scheme for coupled lumped-distributed interconnect simulation.
250-253
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- Fenghao Mu, Christer Svensson:
Methodology of layout based schematic and its usage in efficient high performance CMOS design.
254-257
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- Haksu Kim, Dian Zhou:
An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles.
258-261
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- D. Stroobannt:
PIN count prediction in ratio cut partitioning for VLSI and ULSI.
262-265
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- T. Watanabe, H. Asai:
Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method.
266-269
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- Yen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh:
A quadratic programming method for interconnection crosstalk minimization.
270-273
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- Yiqun Lin, R. Lomenick, R. Lowther, Wenhua Ni, W. Rafie-Hibner, O. Ruiz, J. Furino:
Interconnect model generation tool.
274-277
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- A. Maxim, D. Andreu, M. Cousineau, J. Boucher:
A novel SPICE behavioral macromodel of operational amplifiers including a high accuracy description of frequency characteristics.
278-281
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- Robert H. Caverly, N. Quinn:
A SPICE model for simulating the impedance-frequency characteristics of high frequency PIN switching diodes.
282-285
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- Ecevit Yilmaz, Michael M. Green:
Some standard SPICE dc algorithms revisited: why does SPICE still not converge?
286-289
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- A. Dyes, E. Chan, H. Hofmann, W. Horia, L. Trajkovic:
Simple implementations of homotopy algorithms for finding DC solutions of nonlinear circuits.
290-293
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- Zbigniew Galias:
Proving the existence of periodic solutions using global interval Newton method.
294-297
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- F. Bonani, Marco Gilli:
A harmonic balance approach to bifurcation analysis of limit cycles.
298-301
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- Lidia Daldoss, P. Gubian, Michele Quarantelli:
Transient sensitivity computation in circuit simulation.
302-305
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- M. A. Al-Saleh, M. Mir:
A modified univariate search algorithm.
306-309
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- L. A. MacEachern:
Constrained circuit optimization via library table genetic algorithms.
310-313
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- Yaser M. A. Khalifa, David H. Horrocks:
Isomorphism elimination for the enhancement of genetically generated analog circuits.
314-317
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- N. Shinomiya, H. Watanabe:
Distributed meta-heuristic method for network optimization problems in information network.
318-321
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- Mikio Hasegawa, Tohru Ikeguchi, Kazuyuki Aihara:
A novel approach for combinatorial optimization problems using chaotic neurodynamics.
322-325
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- Maitham Shams, Mohamed I. Elmasry:
A formulation for quick evaluation and optimization of digital CMOS circuits.
326-329
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- Wei Wang, M. N. S. Swamy, M. Omair Ahmad, Yuke Wang:
A high-speed residue-to-binary converter and a scheme for its VLSI implementation.
330-333
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- Rajamohana Hegde, Naresh R. Shanbhag:
Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI.
334-337
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- S. Hranilovic, D. A. Johns:
A multilevel modulation scheme for high-speed wireless infrared communications.
338-341
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- Chi Wai Yung, Hung Fai Fu, Chi-Ying Tsui, Roger S. Cheng, D. George:
Unequal error protection for wireless transmission of MPEG audio.
342-345
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- V. Borich, J. East, G. Haddad:
A fixed-point harmonic balance approach for circuit simulation under modulated carrier excitation.
346-349
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- Roman Genov, Gert Cauwenberghs:
16-channel single-chip current-mode track-and-hold acquisition system with 100 dB dynamic range.
350-353
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- S. Nagavarapu, J. Yan, E. K. F. Lee, Randall L. Geiger:
An asynchronous data recovery/retransmission technique with foreground DLL calibration.
354-357
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- Meghanad D. Wagh, Chien-In Henry Chen:
High-level design synthesis with redundancy removal for high speed testable adders.
358-361
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- Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri:
A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis.
362-365
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- Akihisa Yamada, Koichi Nishida, Ryoji Sakurai, Andrew Kay, Toshio Nomura, Takashi Kambe:
Hardware synthesis with the Bach system.
366-369
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- J. O. Dedou, Daniel Chillet, Olivier Sentieys:
Behavioral synthesis of asynchronous systems: a methodology.
370-373
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- Xiaowei Li, Paul Y. S. Cheung:
An approach to behavioral synthesis for loop-based BIST.
374-377
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- Z. X. Shen, C. C. Jong:
A lower bound on general minimal resource interval scheduling with arbitrary component selection.
378-381
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- M. B. Maaz, Magdy A. Bayoumi:
A non-zero clock skew scheduling algorithm for high speed clock distribution network.
382-385
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- Ali Shatnawi, M. Omair Ahmad, M. N. S. Swamy:
Scheduling of DSP data flow graphs onto multiprocessors for maximum throughput.
386-389
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- Ching-Han Tsai, Sung-Mo Kang:
Macrocell placement with temperature profile optimization.
390-393
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- Frank Schmiedle, Rolf Drechsler, Bernd Becker:
Exact channel routing using symbolic representation.
394-397
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- Paul Y. S. Cheung, S. K. Yeung, W. L. Ko:
A new optimization model for VLSI placement algorithms.
398-403
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- Yehea I. Ismail, Eby G. Friedman:
Repeater insertion in RLC lines for minimum propagation delay.
404-407
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- X. Zeng, J. Guan, W. Q. Zhao, P. S. Tang, D. Zhou:
A constraint-based placement refinement method for CMOS analog cell layout.
408-411
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- Markus Wolf, Ulrich Kleine:
Reliability driven module generation for analog layouts.
412-415
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- Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang:
A cell selection strategy for low power applications.
416-419
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- Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low power synthesis of sum-of-product computation in DSP algorithms.
420-423
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- Franc Brglez, Rolf Drechsler:
Design of experiments in CAD: context and new data sets for ISCAS'99.
424-427
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- Michael D. Hutton, Jonathan Rose:
Equivalence classes of clone circuits for physical-design benchmarking.
428-431
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- Debabrata Ghosh, Franc Brglez:
Equivalence classes of circuit mutants for experimental design.
432-435
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- Wolfgang Günther, Rolf Drechsler:
Creating hard problem instances in logic synthesis using exact minimization.
436-439
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- Hemang Lavana, Franc Brglez, Robert B. Reese:
User-configurable experimental design flows on the web: the ISCAS'99 experiments.
440-443
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- Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh:
Evaluating iterative improvement heuristics for bigraph crossing minimization.
444-447
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- Michael D. Hutton, Jonathan Rose:
Applications of clone circuits to issues in physical-design.
448-451
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- Justin E. Harlow III, Franc Brglez:
Mirror, mirror, on the wall...is the new release any different at all? [BDDs].
452-455
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- S. J. Krolikoski, Frank Schirrmeister, B. Salefski, J. Rowson, Grant Martin:
Methodology and technology for virtual component driven hardware/software co-design on the system-level.
456-459
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- P. P. Jain:
Cost-effective co-verification using RTL-accurate C models.
460-463
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- G. J. Bunza:
Towards systems integration in a virtual environment: small steps, big results, and complications to come for embedded systems engineering in the next millennium.
464-467
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- Graham R. Hellestrand:
Designing system on a chip products using systems engineering tools.
468-473
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- J. Kenney:
Co-verification as risk management: minimizing the risk of incorporating a new processor in your next embedded system design.
474-477
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- S. Davis, J. Braatz, J. Clement, D. Honda:
Advanced instrument controller ASIC.
478-480
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- Andrea Alimonda, Salvatore Carta, Luigi Raffo:
A modular digital VLSI architecture for stereo depth estimation in industrial applications.
481-484
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- Gyung-Hae Han, Hwa-Young Yi, Bum-Suk Go, Dong-Geun Lee, In-Haeng Cho, Dong-Il Oh:
A new ASIC for washer controller.
485-488
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- D. J. Alladi, M. L. Nagy, S. L. Gaverick:
An IC for closed-loop control of a micromotor with an electrostatically levitated rotor.
489-492
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- Mohamad Rahal, J. Winter, John Taylor, Nick Donaldson:
Interference reduction in nerve cuff electrode recordings-a new approach.
493-496
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- Jong-Nam Kim, Tae-Sun Choi:
Fast motion estimation using UESA, threshold-half-stop and adaptive partial sum scan from gradient magnitude.
497-500
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- M. Salerno, F. Sargeni, V. Bonaiuto, Sergio Taraglio, Andrea Zanela:
A dedicated hardware system for CNN stereo vision.
501-504
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- Wen-Cheng Yen, Chung-Yu Wu:
A new compact neuron-bipolar cellular neural network structure with adjustable neighborhood layers and high integration level.
505-508
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- V. K. Jain, S. Shrivastava, A. D. Snider, D. Damerow, D. Chester:
Hardware implementation of a nonlinear processor.
509-514
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Copyright © Sat May 16 23:25:22 2009
by Michael Ley (ley@uni-trier.de)
