ICCD 1994:
Cambridge,
MA,
USA
Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994.
IEEE Computer Society 1994, ISBN 0-8186-6565-3 BibTeX
@proceedings{DBLP:conf/iccd/1994,
title = {Proceedings 1994 IEEE International Conference on Computer Design:
VLSI in Computer {\&} Processors, ICCD '94, Cambridge, MA, USA,
October 10-12, 1994},
publisher = {IEEE Computer Society},
year = {1994},
isbn = {0-8186-6565-3},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
CAD Plenary
- Neil Weste:
OK, If These CAD Tools Are So Great, Why Isn't My Chip Design On Schedule?.
2-8 BibTeX
VLSI Plenary
D&T Plenary
Combinational Logic Synthesis
Memory Architectures
Parallel Processing and Fault Tolerance
- M. Morioka, K. Kurosawa, S. Miura, T. Nakamikawa, S. Ishikawa:
Design and Evaluation of the High Performance Multi-Processor Server.
66-69 BibTeX
- Sangho Ha, Junghwan Kim, Eunha Rho, Yoonhee Nah, Sangyong Han, Daejoon Hwang, Heunghwan Kim, Seung Ho Cho:
A Massively Parallel Multithreaded Architecture: DAVRID.
70-74 BibTeX
- Hussain Al-Asaad, Mankuan Michael Vai, James Feldman:
Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths.
75-78 BibTeX
- Choong Gun Oh, Hee Yong Youn:
Fault Tolerant Processor Arrays for Nonlinear Shortest Path Problem.
79-83 BibTeX
Synthesis for Testability
Formal Representation
Concurrent Error Detection
Instruction Scheduling
Timing Analysis
Field Programmable Systems
Microprocessor Architecture
- John M. Borkenhagen, Glen H. Handlogten, John D. Irish, Sheldon B. Levenstein:
AS/400TM 64-bit PowerPCTM-Compatible Processor Implementaiton.
192-196 BibTeX
- Mike Gruver, Nghia Phan, Tony Aipperspach, Scott Hilker, Jerry Bartley:
AS/400 PowerPCTM Compatible Semi-Custom Technology.
197-202 BibTeX
- Masahito Matsuo, Hiroyuki Kondo, Yukari Takata, Souichi Kobayashi, Mitsugu Satoh, Toyohiko Yoshida, Yuichi Saitoh, Jun-ichi Hinata:
A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface.
203-210 BibTeX
Asynchronous Circuit Design
State-Based Formal Verification
Sequential Logic Synthesis
Computer-Aided Embedded System Design
Bist/Testability Analysis
Architectural Building Blocks
Applications of High-Level Synthesis
Superscalar Processor Performance
Test Generation
System Technology
Timing Analysis and Optimization
PowerPC Alliance
Embedded System Design Examples
Asynchronous Circuit Synthesis
Industrial Applications of Formal Methods
- Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen:
Architectural Verification of Processors Using Symbolic Instruction Graphs.
454-459 BibTeX
- Mark Genoe, Luc J. M. Claesen, Hugo De Man:
A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis.
460-463 BibTeX
- Huy Nam Nguyen, J. P. Tual, L. Ducousso, M. Thill, P. Vallet:
The Structured Logic CAD Suite Used on the DPS7000 System.
464-467 BibTeX
Field Programmable Gate Array Architectures
Software Testing
Computer Arithmetic
Techniques Used in Production Logic Synthesis Systems
Embedded Systems Plenary
Special Purpose VLSI Architectures
High Speed Interconnect Analysis
Scheduling and Allocation in High-Level Synthesis
MCM Applications and Design Methodologies
- Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai:
Optimal Design of Self-Damped Lossy Transmission Lines for Multichip Modules.
594-598 BibTeX
- James Loy, Atul Garg, Mukkai S. Krishnamoorthy, John F. McDonald:
Differential Routing of MCMs - CIF: The Ideal Bifurcation Medium.
599-603 BibTeX
- Mohammad Hossain Heydari, Ioannis G. Tollis, Chunliang Xia:
Improved Techniques for MCM Layer Assignment.
604-607 BibTeX
- Atul Garg, T.-L. Sham, Hans J. Greub, James Loy, Jack F. McDonald:
Thermal Design of an Advanced Multichip Module for a RISC Processor.
608-611 BibTeX
CMOS Circuit Techniques
Copyright © Sat May 16 23:16:39 2009
by Michael Ley (ley@uni-trier.de)