2009 |
9 | EE | Amir-Mohammad Rahmani,
I. Kamali,
Pejman Lotfi-Kamran,
Ali Afzali-Kusha,
Saeed Safari:
Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips.
VLSI Design 2009: 157-162 |
2008 |
8 | EE | Pejman Lotfi-Kamran,
Masoud Daneshtalab,
Caro Lucas,
Zainalabedin Navabi:
BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs.
DATE 2008: 1408-1413 |
7 | EE | Pejman Lotfi-Kamran,
Mehran Massoumi,
Mohammad Mirzaei,
Zainalabedin Navabi:
Enhanced TED: A New Data Structure for RTL Verification.
VLSI Design 2008: 481-486 |
6 | EE | Pejman Lotfi-Kamran,
Amir-Mohammad Rahmani,
Ali-Asghar Salehpour,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Stall Power Reduction in Pipelined Architecture Processors.
VLSI Design 2008: 541-546 |
2007 |
5 | EE | Mohammad Hosseinabady,
Mohammad Hossein Neishaburi,
Pejman Lotfi-Kamran,
Zainalabedin Navabi:
A UML Based System Level Failure Rate Assessment Technique for SoC Designs.
VTS 2007: 243-248 |
4 | EE | Mohammad Hosseinabady,
Pejman Lotfi-Kamran,
Zainalabedin Navabi:
Low test application time resource binding for behavioral synthesis.
ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
2006 |
3 | EE | Mohammad Hosseinabady,
Pejman Lotfi-Kamran,
Giorgio Di Natale,
Stefano Di Carlo,
Alfredo Benso,
Paolo Prinetto:
Single-Event Upset Analysis and Protection in High Speed Circuits.
European Test Symposium 2006: 29-34 |
2005 |
2 | EE | Pejman Lotfi-Kamran,
Mohammad Hosseinabady,
Hamid Shojaei,
Mehran Massoumi,
Zainalabedin Navabi:
TED+: a data structure for microprocessor verification.
ASP-DAC 2005: 567-572 |
1 | EE | Arash Hooshmand,
Saeed Shamshiri,
Mohammad Alisafaee,
Bijan Alizadeh,
Pejman Lotfi-Kamran,
Mostafa Naderi,
Zainalabedin Navabi:
Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams.
ISCAS (1) 2005: 424-427 |