Boxue Yin

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2009

2 EE Zhen Chen, Dong Xiang, Boxue Yin: A power-effective scan architecture using scan flip-flops clustering and post-generation filling. ACM Great Lakes Symposium on VLSI 2009: 517-522

1 EE Boxue Yin, Dong Xiang, Zhen Chen: New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. VLSI Design 2009: 221-226

2009
2	EE	Zhen Chen, Dong Xiang, Boxue Yin: A power-effective scan architecture using scan flip-flops clustering and post-generation filling. ACM Great Lakes Symposium on VLSI 2009: 517-522
1	EE	Boxue Yin, Dong Xiang, Zhen Chen: New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. VLSI Design 2009: 221-226

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