2009 |
11 | EE | Suresh Srinivasan,
Sanu Mathew,
Vasantha Erraguntla,
Ram Krishnamurthy:
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS.
VLSI Design 2009: 301-306 |
2008 |
10 | EE | Suresh Srinivasan,
Krishnan Ramakrishnan,
Prasanth Mangalagiri,
Yuan Xie,
Vijaykrishnan Narayanan,
Mary Jane Irwin,
Karthik Sarpatwari:
Toward Increasing FPGA Lifetime.
IEEE Trans. Dependable Sec. Comput. 5(2): 115-127 (2008) |
2007 |
9 | EE | Suresh Srinivasan,
Prasanth Mangalagiri,
Yuan Xie,
Narayanan Vijaykrishnan:
FPGA routing architecture analysis under variations.
ICCD 2007: 152-157 |
8 | EE | Aman Gayasen,
Suresh Srinivasan,
Narayanan Vijaykrishnan,
Mahmut T. Kandemir:
Design of power-aware FPGA fabrics.
IJES 3(1/2): 52-64 (2007) |
2006 |
7 | EE | Balaji Vaidyanathan,
Suresh Srinivasan,
Yuan Xie,
Narayanan Vijaykrishnan,
Rong Luo:
Leakage Optimized DECAP Design for FPGAs.
APCCAS 2006: 960-963 |
6 | EE | Suresh Srinivasan,
Prasanth Mangalagiri,
Yuan Xie,
Narayanan Vijaykrishnan,
Karthik Sarpatwari:
FLAW: FPGA lifetime awareness.
DAC 2006: 630-635 |
5 | EE | Ing-Chao Lin,
Suresh Srinivasan,
Narayanan Vijaykrishnan,
Nagu R. Dhanwada:
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures.
ISQED 2006: 775-780 |
4 | EE | Suresh Srinivasan,
Narayanan Vijaykrishnan:
Variation Aware Placement for FPGAs.
ISVLSI 2006: 422-423 |
2005 |
3 | EE | Suresh Srinivasan,
Aman Gayasen,
Narayanan Vijaykrishnan,
Tim Tuan:
Leakage control in FPGA routing fabric.
ASP-DAC 2005: 661-664 |
2 | EE | Suresh Srinivasan,
Lin Li,
Narayanan Vijaykrishnan:
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures.
DATE 2005: 218-223 |
2004 |
1 | EE | Suresh Srinivasan,
Aman Gayasen,
Narayanan Vijaykrishnan,
Mahmut T. Kandemir,
Yuan Xie,
Mary Jane Irwin:
Improving soft-error tolerance of FPGA configuration bits.
ICCAD 2004: 107-110 |