2009 |
13 | EE | Tomohiro Nishida,
Susumu Kanemune,
Yukio Idosaka,
Mitaro Namiki,
Tim Bell,
Yasushi Kuno:
A CS unplugged design pattern.
SIGCSE 2009: 231-235 |
12 | EE | Kimiyoshi Usami,
Toshiaki Shirai,
Tasunori Hashida,
Hiroki Masuda,
Seidai Takeda,
Mitsutaka Nakata,
Naomi Seki,
Hideharu Amano,
Mitaro Namiki,
Masashi Imai,
Masaaki Kondo,
Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
VLSI Design 2009: 381-386 |
2008 |
11 | EE | Naomi Seki,
Lei Zhao,
Jo Kei,
Daisuke Ikebuchi,
Yu Kojima,
Yohei Hasegawa,
Hideharu Amano,
Toshihiro Kashima,
Seidai Takeda,
Toshiaki Shirai,
Mitsutaka Nakata,
Kimiyoshi Usami,
Tetsuya Sunata,
Jun Kanai,
Mitaro Namiki,
Masaaki Kondo,
Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000.
ICCD 2008: 612-617 |
2007 |
10 | | Jun Kanai,
Mitaro Namiki,
Kuniyasu Suzaki,
Toshiki Yagi:
Mobile Thin-Client System with Fault Tolerance and Scalability by.
PDPTA 2007: 207-213 |
2006 |
9 | | Jun Kanai,
Takuro Mori,
Takeshi Araki,
Noboru Tanabe,
Hironori Nakajo,
Mitaro Namiki:
Implementation of PC Cluster System with Memory Mapped File by Commodity OS.
PDPTA 2006: 902-908 |
8 | | Ippei Tate,
Yoshiyasu Ogasawara,
Mikiko Sato,
Koichi Sasada,
Kaname Uchikura,
Kazunari Asano,
Satoshi Watanabe,
Mitaro Namiki,
Hironori Nakajo:
A Model of Implementable SMT Processor on FPGA.
PDPTA 2006: 909-915 |
7 | | Yoshiyasu Ogasawara,
Ippei Tate,
Satoshi Watanabe,
Mikiko Sato,
Koichi Sasada,
Kaname Uchikura,
Kazunari Asano,
Mitaro Namiki,
Hironori Nakajo:
Towards Reconfigurable Cache Memory for a Multithreaded Processor.
PDPTA 2006: 916-924 |
2005 |
6 | | Yoshiyasu Ogasawara,
Norito Kato,
Masanori Yamato,
Mikiko Sato,
Koichi Sasada,
Kaname Uchikura,
Mitaro Namiki,
Hironori Nakajo:
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.
PDPTA 2005: 447-453 |
5 | | Kaname Uchikura,
Koichi Sasada,
Mikiko Sato,
Masanori Yamato,
Norito Kato,
Hironori Nakajo,
Mitaro Namiki:
Development of a Thread Scheduler for SMT Processor Architecture.
PDPTA 2005: 454-460 |
2004 |
4 | | Norito Kato,
Masanori Yamato,
Osamu Tujimoto,
Mikiko Sato,
Koichi Sasada,
Kaname Uchikura,
Mitaro Namiki,
Hironori Nakajo:
Dynamic Allocation of Physical Register Banks for an SMT Processor.
PDPTA 2004: 317-323 |
2003 |
3 | | Mikiko Sato,
Koichi Sasada,
Shoji Kawahara,
Norito Kato,
Masanori Yamato,
Hironori Nakajo,
Mitaro Namiki:
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture.
PDPTA 2003: 1669-1675 |
2 | | Hironori Nakajo,
Masanori Yamato,
Shoji Kawahara,
Norito Kato,
Koichi Sasada,
Mikiko Sato,
Mitaro Namiki:
Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.
PDPTA 2003: 1775-1781 |
1 | | Koichi Sasada,
Mikiko Sato,
Shoji Kawahara,
Norito Kato,
Masanori Yamato,
Hironori Nakajo,
Mitaro Namiki:
Implementation and Evaluation of a Thread Library for Multithreaded Architecture.
PDPTA 2003: 609-615 |