2009 |
19 | EE | Kimiyoshi Usami,
Toshiaki Shirai,
Tasunori Hashida,
Hiroki Masuda,
Seidai Takeda,
Mitsutaka Nakata,
Naomi Seki,
Hideharu Amano,
Mitaro Namiki,
Masashi Imai,
Masaaki Kondo,
Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
VLSI Design 2009: 381-386 |
2008 |
18 | EE | Naomi Seki,
Lei Zhao,
Jo Kei,
Daisuke Ikebuchi,
Yu Kojima,
Yohei Hasegawa,
Hideharu Amano,
Toshihiro Kashima,
Seidai Takeda,
Toshiaki Shirai,
Mitsutaka Nakata,
Kimiyoshi Usami,
Tetsuya Sunata,
Jun Kanai,
Mitaro Namiki,
Masaaki Kondo,
Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000.
ICCD 2008: 612-617 |
2007 |
17 | EE | Hiroshi Sasaki,
Yoshimichi Ikeda,
Masaaki Kondo,
Hiroshi Nakamura:
An intra-task dvfs technique based on statistical analysis of hardware events.
Conf. Computing Frontiers 2007: 123-130 |
16 | EE | Ryo Watanabe,
Masaaki Kondo,
Masashi Imai,
Hiroshi Nakamura,
Takashi Nanya:
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.
DATE 2007: 797-802 |
15 | EE | Ryo Watanabe,
Masaaki Kondo,
Hiroshi Nakamura,
Takashi Nanya:
Power reduction of chip multi-processors using shared resource control cooperating with DVFS.
ICCD 2007: 615-622 |
14 | EE | Masaaki Kondo,
Yoshimichi Ikeda,
Hiroshi Nakamura:
A High Performance Cluster System Design by Adaptie Power Control.
IPDPS 2007: 1-8 |
2006 |
13 | EE | Hiroshi Sasaki,
Masaaki Kondo,
Hiroshi Nakamura:
Energy-efficient dynamic instruction scheduling logic through instruction grouping.
ISLPED 2006: 43-48 |
12 | EE | Kouichi Watanabe,
Masashi Imai,
Masaaki Kondo,
Hiroshi Nakamura,
Takashi Nanya:
Design Method of High Performance and Low Power Functional Units Considering Delay Variations.
IEICE Transactions 89-A(12): 3519-3528 (2006) |
2005 |
11 | EE | Masaaki Kondo,
Hiroshi Nakamura:
A Small, Fast and Low-Power Register File by Bit-Partitioning.
HPCA 2005: 40-49 |
10 | EE | Hiroshi Sasaki,
Masaaki Kondo,
Hiroshi Nakamura:
Dynamic Instruction Cascading on GALS Microprocessors.
PATMOS 2005: 30-39 |
2004 |
9 | EE | Motonobu Fujita,
Masaaki Kondo,
Hiroshi Nakamura:
Data Movement Optimization for Software-Controlled On-Chip Memory.
Interaction between Compilers and Computer Architectures 2004: 120-127 |
8 | EE | Masaaki Kondo,
Hiroshi Nakamura:
Dynamic Processor Throttling for Power Efficient Computations.
PACS 2004: 120-134 |
7 | EE | Hiroshi Nakamura,
Takuro Hayashida,
Masaaki Kondo,
Yuya Tajima,
Masashi Imai,
Takashi Nanya:
Skewed Checkpointing for Tolerating Multi-Node Failures.
SRDS 2004: 116-125 |
6 | EE | Chikafumi Takahashi,
Masaaki Kondo,
Taisuke Boku,
Daisuke Takahashi,
Hiroshi Nakamura,
Mitsuhisa Sato:
SCIMA-SMP: on-chip memory processor architecture for SMP.
WMPI 2004: 121-128 |
2002 |
5 | EE | T. Ohneda,
Masaaki Kondo,
Masashi Imai,
Hiroshi Nakamura:
Design and evaluation of high performance microprocessor with reconfigurable on-chip memory.
APCCAS (1) 2002: 211-216 |
4 | EE | Masaaki Kondo,
Mitsugu Iwamoto,
Hiroshi Nakamura:
Cache Line Impact on 3D PDE Solvers.
ISHPC 2002: 301-309 |
3 | EE | Masaaki Kondo,
Motonobu Fujita,
Hiroshi Nakamura:
Software-controlled on-chip memory for high-performance and low-power computing.
SIGARCH Computer Architecture News 30(3): 7-8 (2002) |
2000 |
2 | EE | Masaaki Kondo,
Hideki Okawara,
Hiroshi Nakamura,
Taisuke Boku:
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing.
ICCD 2000: 105- |
1 | EE | Hiroshi Nakamura,
Masaaki Kondo,
Taisuke Boku:
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing.
Intelligent Memory Systems 2000: 15-32 |