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| 2009 | ||
|---|---|---|
| 5 | EE | Saurabh K. Tiwary, Amith Singhee, Vikas Chandra: Robust Circuit Design: Challenges and Solutions. VLSI Design 2009: 41-42 |
| 2007 | ||
| 4 | EE | Saurabh K. Tiwary, Joel R. Phillips: WAVSTAN: waveform based variational static timing analysis. DATE 2007: 1000-1005 |
| 2006 | ||
| 3 | EE | Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar: Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. DAC 2006: 31-36 |
| 2 | EE | Saurabh K. Tiwary, Rob A. Rutenbar: Faster, parametric trajectory-based macromodels via localized linear reductions. ICCAD 2006: 876-883 |
| 2005 | ||
| 1 | EE | Saurabh K. Tiwary, Rob A. Rutenbar: Scalable trajectory methods for on-demand analog macromodel extraction. DAC 2005: 403-408 |
| 1 | Vikas Chandra | [5] |
| 2 | Joel R. Phillips | [4] |
| 3 | Rob A. Rutenbar | [1] [2] [3] |
| 4 | Amith Singhee | [5] |
| 5 | Pragati K. Tiwary | [3] |