| 2009 |
|---|
| 7 | EE | Koustav Bhattacharya,
Nagarajan Ranganathan:
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations.
ISQED 2009: 388-393 |
| 6 | EE | Koustav Bhattacharya,
Nagarajan Ranganathan:
RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits.
VLSI Design 2009: 453-458 |
| 2008 |
|---|
| 5 | EE | Koustav Bhattacharya,
Nagarajan Ranganathan:
A linear programming formulation for security-aware gate sizing.
ACM Great Lakes Symposium on VLSI 2008: 273-278 |
| 4 | EE | Koustav Bhattacharya,
Nagarajan Ranganathan:
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power.
ISLPED 2008: 99-104 |
| 2007 |
|---|
| 3 | EE | Koustav Bhattacharya,
Soontae Kim,
Nagarajan Ranganathan:
Improving the reliability of on-chip L2 cache using redundancy.
ICCD 2007: 224-229 |
| 2004 |
|---|
| 2 | | Jayanta Basak,
Koustav Bhattacharya,
Santanu Chaudhury:
Multi Example Based Image Retrieval: An ICA Based Approach.
ICVGIP 2004: 151-157 |
| 1 | | Koustav Bhattacharya,
Santanu Chaudhury,
Jayanta Basak:
Video Summarization: A Machine Learning Based Approach.
ICVGIP 2004: 429-434 |
