| 2009 |
|---|
| 8 | EE | Jawar Singh,
Jimson Mathew,
Saraju P. Mohanty,
Dhiraj K. Pradhan:
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.
VLSI Design 2009: 307-312 |
| 2008 |
|---|
| 7 | EE | Jimson Mathew,
Jawar Singh,
Abusaleh M. Jabir,
Mohammad Hosseinabady,
Dhiraj K. Pradhan:
Fault tolerant bit parallel finite field multipliers using LDPC codes.
ISCAS 2008: 1684-1687 |
| 6 | EE | Jawar Singh,
Jimson Mathew,
Saraju P. Mohanty,
Dhiraj K. Pradhan:
A nano-CMOS process variation induced read failure tolerant SRAM cell.
ISCAS 2008: 3334-3337 |
| 5 | EE | Yi Xin Su,
Jimson Mathew,
Jawar Singh,
Dhiraj K. Pradhan:
Pseudo parallel architecture for AES with error correction.
SoCC 2008: 187-190 |
| 4 | EE | Jawar Singh,
Jimson Mathew,
Dhiraj K. Pradhan,
Saraju P. Mohanty:
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.
SoCC 2008: 243-246 |
| 3 | EE | Jawar Singh,
Jimson Mathew,
Dhiraj K. Pradhan,
Saraju P. Mohanty:
Failure analysis for ultra low power nano-CMOS SRAM under process variations.
SoCC 2008: 251-254 |
| 2007 |
|---|
| 2 | EE | Babita R. Jose,
P. Mythili,
Jawar Singh,
Jimson Mathew:
A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards.
ICIT 2007: 127-132 |
| 1 | EE | Jawar Singh,
Jimson Mathew,
Mohammad Hosseinabady,
Dhiraj K. Pradhan:
Single Event Upset Detection and Correction.
ICIT 2007: 13-18 |
