| 2009 |
|---|
| 10 | EE | Daniel Große,
Robert Wille,
Ulrich Kühne,
Rolf Drechsler:
Contradictory antecedent debugging in bounded model checking.
ACM Great Lakes Symposium on VLSI 2009: 173-176 |
| 9 | EE | Robert Wille,
Daniel Große,
Gerhard W. Dueck,
Rolf Drechsler:
Reversible Logic Synthesis with Output Permutation.
VLSI Design 2009: 189-194 |
| 2008 |
|---|
| 8 | EE | Robert Wille,
Hoang M. Le,
Gerhard W. Dueck,
Daniel Große:
Quantified Synthesis of Reversible Logic.
DATE 2008: 1015-1020 |
| 7 | EE | Daniel Große,
Robert Wille,
Robert Siegmund,
Rolf Drechsler:
Contradiction Analysis for Constraint-based Random Simulation.
FDL 2008: 130-135 |
| 6 | EE | Daniel Große,
Robert Wille,
Gerhard W. Dueck,
Rolf Drechsler:
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares.
ISMVL 2008: 214-219 |
| 5 | EE | Robert Wille,
Daniel Große,
Lisa Teuber,
Gerhard W. Dueck,
Rolf Drechsler:
RevLib: An Online Resource for Reversible Functions and Reversible Circuits.
ISMVL 2008: 220-225 |
| 4 | EE | Robert Wille,
Daniel Große,
Mathias Soeken,
Rolf Drechsler:
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability.
ISVLSI 2008: 411-416 |
| 2007 |
|---|
| 3 | EE | Robert Wille,
Daniel Große:
Fast exact Toffoli network synthesis of reversible logic.
ICCAD 2007: 60-64 |
| 2 | EE | Robert Wille,
Görschwin Fey,
Daniel Große,
Stephan Eggersglüß,
Rolf Drechsler:
SWORD: A SAT like prover using word level information.
VLSI-SoC 2007: 88-93 |
| 1993 |
|---|
| 1 | | Kevin Bolding,
Sen-Ching Cheung,
Sung-Eun Choi,
Carl Ebeling,
Soha Hassoun,
Ton Anh Ngo,
Robert Wille:
The chaos router chip: design and implementation of an adaptive router.
VLSI 1993: 311-320 |
