| 2009 |
|---|
| 6 | EE | Sreehari Veeramachaneni,
A. Mahesh Kumar,
Venkat Tummala,
M. B. Srinivas:
Design of a Low Power, Variable-Resolution Flash ADC.
VLSI Design 2009: 117-122 |
| 2008 |
|---|
| 5 | EE | Sreehari Veeramachaneni,
Kirthi M. Krishna,
Prateek G. V.,
Subroto S.,
Bharat S.,
M. B. Srinivas:
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.
VLSI Design 2008: 547-552 |
| 2007 |
|---|
| 4 | EE | Sreehari Veeramachaneni,
Lingamneni Avinash,
Kirthi M. Krishna,
M. B. Srinivas:
Novel architectures for efficient (m, n) parallel counters.
ACM Great Lakes Symposium on VLSI 2007: 188-191 |
| 3 | EE | Sreehari Veeramachaneni,
Kirthi M. Krishna,
Lingamneni Avinash,
Reddy Puppala Sreekanth,
M. B. Srinivas:
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.
ISCAS 2007: 3271-3274 |
| 2 | EE | Sreehari Veeramachaneni,
Kirthi M. Krishna,
Lingamneni Avinash,
Reddy Puppala Sreekanth,
M. B. Srinivas:
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.
ISVLSI 2007: 343-350 |
| 1 | EE | Sreehari Veeramachaneni,
Kirthi M. Krishna,
Lingamneni Avinash,
Reddy Puppala Sreekanth,
M. B. Srinivas:
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.
VLSI Design 2007: 324-329 |
