| 2009 |
|---|
| 3 | EE | Jithendra Srinivas,
Madhusudan Rao,
Sukumar Jairam,
H. Udayakumar,
Jagdish C. Rao:
Clock gating effectiveness metrics: Applications to power optimization.
ISQED 2009: 482-487 |
| 2 | EE | R. Venkatraman,
Shrikrishna Pundoor,
Arun Koithyar,
Madhusudan Rao,
Jagdish C. Rao:
Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions.
VLSI Design 2009: 525-530 |
| 2008 |
|---|
| 1 | EE | Sukumar Jairam,
Madhusudan Rao,
Jithendra Srinivas,
Parimala Vishwanath,
H. Udayakumar,
Jagdish C. Rao:
Clock gating for power optimization in ASIC design cycle theory & practice.
ISLPED 2008: 307-308 |
