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2009 | ||
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2 | EE | Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar: A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. VLSI Design 2009: 373-378 |
2007 | ||
1 | EE | Vijay Khawshe, Pravin V. Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara, Manish Jain, Navin Mishra, Abhijit Abhyankar: A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL. VLSI Design 2007: 141-145 |
1 | Abhijit Abhyankar | [1] [2] |
2 | Kunal Desai | [2] |
3 | Prateek Goyal | [2] |
4 | Manish Jain | [1] |
5 | Vijay Khawshe | [1] [2] |
6 | Vijay Krishna | [2] |
7 | Pravin V. Kumar | [1] |
8 | Mahabaleshwara | [1] |
9 | Navin Mishra | [1] |
10 | Rajkumar Palwai | [2] |
11 | Kashinath Prabhu | [2] |
12 | Kashi Prabu | [1] |
13 | Leneesh Raghavan | [2] |
14 | Renu Rangnekar | [1] [2] |
15 | M. Thrivikraman | [2] |
16 | Pravin Kumar Venkatesan | [2] |