18. FPL 2008:
Heidelberg,
Germany
FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008.
IEEE 2008 BibTeX
Modelling
Encryption Applications
Networks on Chip I
Analysis of Reconfigurability
Image and Video Processing
FPGA Architecture
Dynamic Reconfiguration
- Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich:
No-break dynamic defragmentation of reconfigurable devices.
113-118
Electronic Edition (link) BibTeX
- Dirk Koch, Christian Beckhoff, Jürgen Teich:
ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS.
119-124
Electronic Edition (link) BibTeX
- Jorge Suris, Cameron Patterson, Peter Athanas:
An efficient run-time router for connecting modules in FPGAS.
125-130
Electronic Edition (link) BibTeX
Search and Matching Acceleration
Reconfigurable ASIP Design
Compilers for Reconfigurable Architectures
- Ozana Silvia Dragomir, Todor Stefanov, Koen Bertels:
Loop unrolling and shifting for reconfigurable architectures.
167-172
Electronic Edition (link) BibTeX
- Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. Eggers:
CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures.
173-178
Electronic Edition (link) BibTeX
- Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework.
179-184
Electronic Edition (link) BibTeX
Novel Applications
Reconfigurable Processors
Analysis of Reconfigurability II
- Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
An analytical model describing the relationships between logic architecture and FPGA density.
221-226
Electronic Edition (link) BibTeX
- Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton:
Rapid estimation of power consumption for hybrid FPGAs.
227-232
Electronic Edition (link) BibTeX
- Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-chung Hsu, Arun Kundu, Andrew A. Kennings:
A technique for minimizing power during FPGA placement.
233-238
Electronic Edition (link) BibTeX
Random Number Generation & PLL
Networks on Chip II
- Matthew Shelburne, Cameron Patterson, Peter Athanas, Mark Jones, Brian Martin, Ryan Fong:
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip.
257-262
Electronic Edition (link) BibTeX
- Tamas Malek, Tomás Martínek, Jan Korenek:
GICS: Generic interconnection system.
263-268
Electronic Edition (link) BibTeX
- Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A link removal methodology for Networks-on-Chip on reconfigurable systems.
269-274
Electronic Edition (link) BibTeX
Codesign
FPGA Application in High Energy Physics
- Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch:
ATCA-based computation platform for data acquisition and triggering in particle physics experiments.
287-292
Electronic Edition (link) BibTeX
- Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth:
An FPGA-based high-speed, low-latency trigger processor for high-energy physics.
293-298
Electronic Edition (link) BibTeX
Reconfigurable Processor Arrays
Tools for FPGA Design
High Performance Computing for Financial and Biological Modelling
SPP1148 booth
- Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, T. Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker:
Fine grain reconfigurable architectures.
348
Electronic Edition (link) BibTeX
- Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
Coarse-grained reconfiguration.
349
Electronic Edition (link) BibTeX
- Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll:
Application-specific reconfigurable processors.
350
Electronic Edition (link) BibTeX
- Andreas Schallenberg, Achim Rettberg, Wolfgang Nebel, Franz-Josef Rammig:
Seamless design flow for reconfigurable systems.
351
Electronic Edition (link) BibTeX
- Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf:
Network processors.
352
Electronic Edition (link) BibTeX
- Sebastian Lange, Martin Middendorf:
Hyperreconfigurable architectures.
353
Electronic Edition (link) BibTeX
Synthesis
Algorithm Acceleration
Optimization
Surveys and Trends
- Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard:
Reconfigurable hardware: The holy grail of matching performance with programming productivity.
409-414
Electronic Edition (link) BibTeX
- Edward Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerant methods for reliability in FPGAs.
415-420
Electronic Edition (link) BibTeX
- Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune:
A non-volatile run-time FPGA using thermally assisted switching MRAMS.
421-426
Electronic Edition (link) BibTeX
Reconfigurable Architectures
Design Methods and Tools
- Eoin Creedon, Michael Manzke:
Scalable high performance computing on FPGA clusters using message passing.
443-446
Electronic Edition (link) BibTeX
- Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong:
FPGA interconnect design using logical effort.
447-450
Electronic Edition (link) BibTeX
- Jason Wu, John W. Williams, Neil Bergmann:
An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC.
451-454
Electronic Edition (link) BibTeX
- Marco D. Santambrogio, Vincenzo Rana, Donatella Sciuto:
Operating system support for online partial dynamic reconfiguration management.
455-458
Electronic Edition (link) BibTeX
- Meikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha:
Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory.
459-462
Electronic Edition (link) BibTeX
- Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numerical function generators using bilinear interpolation.
463-466
Electronic Edition (link) BibTeX
Applications
Reconfigurable Architectures
- Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dudek, Thomas Dowrick, Liam McDaid:
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks.
483-486
Electronic Edition (link) BibTeX
- Claudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari Nurmi:
A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck.
487-490
Electronic Edition (link) BibTeX
- Hongbing Fan, Jason Ernst, Yu-Liang Wu:
Customized Reconfigurable Interconnection Networks for multiple application SOCS.
491-494
Electronic Edition (link) BibTeX
- Diana Göhringer, Michael Hübner, Thomas Perschke, Jürgen Becker:
New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach.
495-498
Electronic Edition (link) BibTeX
Design Methods and Tools
- Yasuhiro Ito, Yutaka Sugawara, Mary Inaba, Kei Hiraki:
CVC: The C to RTL compiler for callback-based verification model.
499-502
Electronic Edition (link) BibTeX
- Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera:
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.
503-506
Electronic Edition (link) BibTeX
- Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki:
SAT-based resource binding for reducing critical path delays.
507-510
Electronic Edition (link) BibTeX
- Ralf Joost, Ralf Salomon:
BOUNCE, a new approach to measure sub-nanosecond time intervals.
511-514
Electronic Edition (link) BibTeX
- Stephen McKeown, Roger Woods, John McAllister:
Power efficient DSP datapath configuration methodology for FPGA.
515-518
Electronic Edition (link) BibTeX
Applications
Reconfigurable Architectures
- Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker:
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.
535-538
Electronic Edition (link) BibTeX
- Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez:
Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC.
539-542
Electronic Edition (link) BibTeX
- Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka:
Exploring compact design on high throughput coarse grained reconfigurable architectures.
543-546
Electronic Edition (link) BibTeX
- Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, Jose Nunez-Yanez:
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor.
547-550
Electronic Edition (link) BibTeX
Design Methods and Tools
- Christian Hochberger, Alexander Weiss:
A new methodology for debugging and validation of soft cores.
551-554
Electronic Edition (link) BibTeX
- Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
Convergence analysis of run-time distributed optimization on adaptive systems using game theory.
555-558
Electronic Edition (link) BibTeX
- Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong:
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.
559-562
Electronic Edition (link) BibTeX
- Norbert Abel, Frederik Grüll, Nick Meier, Andreas Beyer, Udo Kebschull:
Parallel hardware objects for dynamically partial reconfiguration.
563-566
Electronic Edition (link) BibTeX
- Hayden Kwok-Hay So, Robert W. Brodersen:
File system access from reconfigurable FPGA hardware processes in BORPH.
567-570
Electronic Edition (link) BibTeX
- Enrique Cantó, Francesc Fons, Mariano López:
Self-recofigurable embedded systems on Spartan-3.
571-574
Electronic Edition (link) BibTeX
Applications
Reconfigurable Architectures
- Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich:
A comparison of embedded reconfigurable video-processing architectures.
587-590
Electronic Edition (link) BibTeX
- Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede:
Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor.
591-594
Electronic Edition (link) BibTeX
- Cesar Pedraza, Emilio Castillo, Javier Castillo, Cristobal Camarero, José Luis Bosque, José I. Martínez, Rafael Menéndez de Llano:
Cluster architecture based on low cost reconfigurable hardware.
595-598
Electronic Edition (link) BibTeX
- Andreas Ehliar, Per Karlström, Dake Liu:
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA.
599-602
Electronic Edition (link) BibTeX
Design Methods and Tools
- Kevin K. Liu, Charles B. Cameron, Antal A. Sarkady:
Comparing throughput and power consumption in both sequential and reconfigurable processors.
603-606
Electronic Edition (link) BibTeX
- Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker:
Data path driven waveform-like reconfiguration.
607-610
Electronic Edition (link) BibTeX
- Wenyin Fu, Katherine Compton:
Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems.
611-614
Electronic Edition (link) BibTeX
- Hanyu Liu, Xiaolei Chen, Yajun Ha:
An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects.
615-618
Electronic Edition (link) BibTeX
- Markus Koester, Wayne Luk, Geoffrey Brown:
A hardware compilation flow for instance-specific VLIW cores.
619-622
Electronic Edition (link) BibTeX
Applications
- Michail Zampetakis, Vasilis Samoladas, Apostolos Dollas:
A reconfigurable accelerator for quantum computations.
623-626
Electronic Edition (link) BibTeX
- Andre Guntoro, Manfred Glesner:
High-performance fpga-based floating-point adder with three inputs.
627-630
Electronic Edition (link) BibTeX
- Panagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytraki, Dionisios N. Pnevmatikatos:
A rate-based prefiltering approach to blast acceleration.
631-634
Electronic Edition (link) BibTeX
- Diego P. Morales, Antonio García, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitan-Vallvey:
Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.
635-638
Electronic Edition (link) BibTeX
- George Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine Leligou:
Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching.
639-642
Electronic Edition (link) BibTeX
Reconfigurable Architectures
Design Methods and Tools
Applications
- Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano:
Practical implementation of a network-based stochastic biochemical simulation system on an FPGA.
663-666
Electronic Edition (link) BibTeX
- Jason R. Villarreal, Walid A. Najjar:
Compiled hardware acceleration of Molecular Dynamics code.
667-670
Electronic Edition (link) BibTeX
- Gang Zhou, Li Li, Harald Michalik:
Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS.
671-674
Electronic Edition (link) BibTeX
- Tim Güneysu, Christof Paar, Gerd Pfeiffer, Manfred Schimmler:
Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis.
675-678
Electronic Edition (link) BibTeX
- Donald G. Bailey, Christopher T. Johnston, Ni Ma:
Connected components analysis of streamed images.
679-682
Electronic Edition (link) BibTeX
Surveys,
Trends and Education
- Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle:
On the design parameters of runtime reconfigurable systems.
683-686
Electronic Edition (link) BibTeX
- Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron Sass:
Teaching FPGA system design via a remote laboratory facility.
687-690
Electronic Edition (link) BibTeX
- Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa:
Towards benchmarking energy efficiency of reconfigurable architectures.
691-694
Electronic Edition (link) BibTeX
PhD Forum Presentations
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by Michael Ley (ley@uni-trier.de)
