| |
| 2008 | ||
|---|---|---|
| 1 | EE | Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsusmi, Vasutan Tunbunheng, Hideharu Amano: Power reduction techniques for Dynamically Reconfigurable Processor Arrays. FPL 2008: 305-310 |
| 1 | Hideharu Amano | [1] |
| 2 | Yohei Hasegawa | [1] |
| 3 | Takuro Nakamura | [1] |
| 4 | Takashi Nishimura | [1] |
| 5 | Yoshiki Saito | [1] |
| 6 | Satoshi Tsutsusmi | [1] |
| 7 | Vasutan Tunbunheng | [1] |