| 2008 |
|---|
| 12 | EE | Kazuya Tanigawa,
Tetsuya Zuyama,
Takuro Uchida,
Tetsuo Hironaka:
Exploring compact design on high throughput coarse grained reconfigurable architectures.
FPL 2008: 543-546 |
| 2007 |
|---|
| 11 | EE | Koh Johguchi,
Hans Jürgen Mattausch,
Tetsushi Koide,
Tetsuo Hironaka:
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words.
IEICE Transactions 90-C(11): 2157-2160 (2007) |
| 2006 |
|---|
| 10 | EE | Koh Johguchi,
Zhaomin Zhu,
Hans Jürgen Mattausch,
Tetsushi Koide,
Tetsuo Hironaka,
Kazuya Tanigawa:
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.
APCCAS 2006: 1297-1300 |
| 9 | EE | Takahiro Sasaki,
Tetsuo Hironaka,
Naoki Nishimura,
Noriyoshi Yoshida:
Scheduling support hardware for multiprocessor system and its evaluations.
Systems and Computers in Japan 37(2): 79-95 (2006) |
| 2005 |
|---|
| 8 | EE | T. Saito,
M. Maeda,
Tetsuo Hironaka,
Kazuya Tanigawa,
Tetsuya Sueyoshi,
K. Aoyama,
Tetsushi Koide,
Hans Jürgen Mattausch:
Design of superscalar processor with multi-bank register file.
ISCAS (4) 2005: 3507-3510 |
| 7 | EE | Takahiro Sasaki,
Tomohiro Inoue,
Nobuhiko Omori,
Tetsuo Hironaka,
Hans Jürgen Mattausch,
Tetsushi Koide:
Chip size and performance evaluations of shared cache for on-chip multiprocessor.
Systems and Computers in Japan 36(9): 1-13 (2005) |
| 2004 |
|---|
| 6 | EE | Tetsuya Sueyoshi,
Hiroshi Uchida,
Hans Jürgen Mattausch,
Tetsushi Koide,
Yosuke Mitani,
Tetsuo Hironaka:
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors.
ASP-DAC 2004: 551-552 |
| 2002 |
|---|
| 5 | EE | Kazuya Tanigawa,
Tetsuo Hironaka,
Akira Kojima,
Noriyoshi Yoshida:
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model.
FPL 2002: 434-443 |
| 2000 |
|---|
| 4 | EE | Naoki Nishimura,
Takahiro Sasaki,
Tetsuo Hironaka:
Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system.
ASP-DAC 2000: 29-30 |
| 3 | | Takahiro Sasaki,
Tetsuo Hironaka,
Seiji Fujino:
Performance Improvements of Thakore's Algorithm with Speculative Execution Technique and Dynamic Task Scheduling.
Informatica (Slovenia) 24(1): (2000) |
| 1993 |
|---|
| 2 | EE | Takashi Hashimoto,
Kazuaki Murakami,
Tetsuo Hironaka,
Hiroto Yasuura:
A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking.
International Conference on Supercomputing 1993: 308-317 |
| 1992 |
|---|
| 1 | EE | Tetsuo Hironaka,
Takashi Hashimoto,
Keizo Okazaki,
Kazuaki Murakami,
Shinji Tomita:
Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture.
ICS 1992: 272-281 |
