| 2008 |
|---|
| 10 | EE | Stanislaw Deniziak,
Robert Tomaszewski:
Rapid Prototyping of NoC Architectures from a SystemC Specification.
DDECS 2008: 104-109 |
| 9 | EE | Stanislaw Deniziak,
Mariusz Wisniewski:
An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs.
DDECS 2008: 22-25 |
| 8 | EE | Stanislaw Deniziak,
Mariusz Wisniewski:
An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation.
FPL 2008: 397-402 |
| 7 | EE | Stanislaw Deniziak,
Adam Gorski:
Hardware/Software Co-synthesis of Distributed Embedded Systems Using Genetic Programming.
ICES 2008: 83-93 |
| 2007 |
|---|
| 6 | | Radoslaw Czarnecki,
Stanislaw Deniziak:
Resource Constrained Co-synthesis of Self-reconfigurable SOPCs.
DDECS 2007: 49-54 |
| 2004 |
|---|
| 5 | EE | Joanna Strug,
Stanislaw Deniziak,
Krzysztof Sapiecha:
Validation of Reactive Embedded Systems against Temporal Requirements.
ECBS 2004: 152-160 |
| 2003 |
|---|
| 4 | EE | Radoslaw Czarnecki,
Stanislaw Deniziak,
Krzysztof Sapiecha:
An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs.
DSD 2003: 443-446 |
| 2001 |
|---|
| 3 | EE | Stanislaw Deniziak,
Krzysztof Sapiecha:
Developing a High-Level Fault Simulation Standard.
IEEE Computer 34(5): 89-90 (2001) |
| 1999 |
|---|
| 2 | EE | Stanislaw Deniziak,
Krzysztof Sapiecha:
High Level Testbench Generation for VHDL Models.
ECBS 1999: 146-151 |
| 1994 |
|---|
| 1 | | Stanislaw Deniziak,
Krzysztof Sapiecha:
Cupland - A Behavioral Level Description Compiler for Designing of PLD/EPLD-Based Systems.
ISCAS 1994: 201-204 |
