2009 | ||
---|---|---|
39 | EE | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378 |
38 | EE | Shigeo Urushidani, Shunji Abe, Yusheng Ji, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto: Design of versatile academic infrastructure for multilayer network services. IEEE Journal on Selected Areas in Communications 27(3): 253-267 (2009) |
2008 | ||
37 | EE | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang: Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC 2008: 55-60 |
36 | EE | Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, Tomohiro Otsuka, Michihiro Koibuchi: Impact of topology and link aggregation on a PC cluster with Ethernet. CLUSTER 2008: 280-285 |
35 | EE | Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi: A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL 2008: 269-274 |
34 | EE | Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano: Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN 2008: 281-288 |
33 | EE | Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston: A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS 2008: 13-22 |
32 | EE | Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano: Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS 2008: 23-32 |
2007 | ||
31 | EE | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL 2007: 383-388 |
30 | EE | Shigeo Urushidani, Jun Matsukata, Kensuke Fukuda, Shunji Abe, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada, Kaori Shimizu, Tomonori Takeda, Ichiro Inoue, Kohei Shiomoto: Layer-1 Bandwidth on Demand Services in SINET3. GLOBECOM 2007: 2286-2291 |
29 | EE | Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji: Investigating QoS Performance on a Testbed Network. ICCCN 2007: 1267-1272 |
28 | EE | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP 2007: 75 |
27 | EE | Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano: Performance Improvement Methodology for ClearSpeed's CSX600. ICPP 2007: 77 |
26 | EE | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS 2007: 1-10 |
25 | EE | Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano: An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks. IEEE Trans. Parallel Distrib. Syst. 18(3): 320-333 (2007) |
24 | EE | Shigeo Urushidani, Shunji Abe, Kensuke Fukuda, Jun Matsukata, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada: Architectural Design of Next-Generation Science Information Network. IEICE Transactions 90-B(5): 1061-1070 (2007) |
23 | EE | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 90-D(12): 1914-1922 (2007) |
2006 | ||
22 | Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano: A Parametric Study of Scalable Interconnects on FPGAs. ERSA 2006: 130-135 | |
21 | EE | Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano: Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. ICPP 2006: 479-486 |
20 | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. ISCA PDCS 2006: 24-31 | |
19 | EE | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA 2006: 207-218 |
18 | EE | Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. IEEE Trans. Parallel Distrib. Syst. 17(12): 1425-1437 (2006) |
2005 | ||
17 | EE | Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. ICPP 2005: 567-576 |
16 | EE | Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280 |
15 | EE | Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato, Michihiro Koibuchi: In-Order Packet Delivery in Interconnection Networks using Adaptive Routing. IPDPS 2005 |
14 | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA 2005: 1343-1349 | |
13 | EE | Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano: Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster. IEEE Trans. Parallel Distrib. Syst. 16(8): 747-759 (2005) |
12 | EE | Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing. IEICE Transactions 88-D(1): 109-118 (2005) |
11 | EE | Michihiro Koibuchi, Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato: Enforcing in-order packet delivery in system area networks with adaptive routing. J. Parallel Distrib. Comput. 65(10): 1223-1236 (2005) |
10 | EE | Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: Path selection algorithm: the strategy for designing deterministic routing from alternative paths. Parallel Computing 31(1): 117-130 (2005) |
2004 | ||
9 | EE | Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura: Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. EUC 2004: 301-311 |
8 | EE | Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. IPDPS 2004 |
2003 | ||
7 | EE | Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano: Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. CLUSTER 2003: 395- |
6 | EE | Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano: Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. ICPP 2003: 527- |
2002 | ||
5 | EE | Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi: Routing Algorithms Based on 2D Turn Model for Irregular Networks. ISPAN 2002: 289-294 |
4 | Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. PDPTA 2002: 1431-1437 | |
2001 | ||
3 | Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: The impact of output selection function on adaptive routing. Computers and Their Applications 2001: 241-246 | |
2 | EE | Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano: L-Turn Routing: An Adaptive Routing in Irregular Networks. ICPP 2001: 383-392 |
1 | Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano: MMLRU Selection Function: An Output Selection Function on Adaptive Routing. ISCA PDCS 2001: 1-6 |