| 2008 |
|---|
| 6 | EE | Roberto Perez-Andrade,
René Cumplido,
Claudia Feregrino Uribe,
Fernando Martin del Campo:
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter.
FPL 2008: 467-470 |
| 5 | EE | Roberto Perez-Andrade,
René Cumplido,
Fernando Martin del Campo,
Claudia Feregrino Uribe:
A Versatile Linear Insertion Sorter Based on a FIFO Scheme.
ISVLSI 2008: 357-362 |
| 2007 |
|---|
| 4 | EE | Alejandro Rojas,
René Cumplido,
Jesús Ariel Carrasco-Ochoa,
Claudia Feregrino Uribe,
José Francisco Martínez Trinidad:
FPGA-Based Architecture for Computing Testors.
IDEAL 2007: 188-197 |
| 2006 |
|---|
| 3 | EE | René Cumplido,
Jesús Ariel Carrasco-Ochoa,
Claudia Feregrino:
On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification.
CIARP 2006: 665-673 |
| 2 | EE | Ignacio Algredo-Badillo,
Claudia Feregrino Uribe,
René Cumplido:
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture.
ICCSA (3) 2006: 456-465 |
| 2005 |
|---|
| 1 | EE | Tomás Balderas-Contreras,
René Cumplido:
High performance encryption cores for 3G networks.
DAC 2005: 240-243 |
