| 2008 |
|---|
| 4 | EE | Kazuya Tanigawa,
Tetsuya Zuyama,
Takuro Uchida,
Tetsuo Hironaka:
Exploring compact design on high throughput coarse grained reconfigurable architectures.
FPL 2008: 543-546 |
| 2006 |
|---|
| 3 | EE | Koh Johguchi,
Zhaomin Zhu,
Hans Jürgen Mattausch,
Tetsushi Koide,
Tetsuo Hironaka,
Kazuya Tanigawa:
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.
APCCAS 2006: 1297-1300 |
| 2005 |
|---|
| 2 | EE | T. Saito,
M. Maeda,
Tetsuo Hironaka,
Kazuya Tanigawa,
Tetsuya Sueyoshi,
K. Aoyama,
Tetsushi Koide,
Hans Jürgen Mattausch:
Design of superscalar processor with multi-bank register file.
ISCAS (4) 2005: 3507-3510 |
| 2002 |
|---|
| 1 | EE | Kazuya Tanigawa,
Tetsuo Hironaka,
Akira Kojima,
Noriyoshi Yoshida:
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model.
FPL 2002: 434-443 |
