| 2008 |
|---|
| 8 | EE | Kenshu Seto,
Yuta Nonaka,
Takuya Maruizumi,
Yasuhiro Shiraki:
SAT-based resource binding for reducing critical path delays.
FPL 2008: 507-510 |
| 7 | EE | Kenshu Seto,
Masahiro Fujita:
Custom Instruction Generation with High-Level Synthesis.
SASP 2008: 14-19 |
| 2007 |
|---|
| 6 | EE | Shigeru Watanabe,
Kenshu Seto,
Y. Ishikawa,
Satoshi Komatsu,
Masahiro Fujita:
Protocol Transducer Synthesis using Divide and Conquer approach.
ASP-DAC 2007: 280-285 |
| 5 | EE | Shanghua Gao,
Kenshu Seto,
Satoshi Komatsu,
Masahiro Fujita:
Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.
IESS 2007: 121-134 |
| 2005 |
|---|
| 4 | | Shanghua Gao,
Kenshu Seto,
Satoshi Komatsu,
Masahiro Fujita:
Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays.
FPT 2005: 137-144 |
| 2003 |
|---|
| 3 | EE | Masahiro Fujita,
Satoshi Komatsu,
Hiroshi Saito,
Kenshu Seto,
Thanyapat Sakunkonchak,
Yoshihisa Kojima:
Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies.
HICSS 2003: 279 |
| 2 | EE | Hiroshi Saito,
Kenshu Seto,
Yoshihisa Kojima,
Satoshi Komatsu,
Masahiro Fujita:
Engineering Changes in Field Modifiable Architectures.
MEMOCODE 2003: 87-94 |
| 2002 |
|---|
| 1 | | Yoshihisa Kojima,
Hiroshi Saito,
Kenshu Seto,
Satoshi Komatsu,
Masahiro Fujita:
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.
IWLS 2002: 103-108 |
