| |
| 2008 | ||
|---|---|---|
| 3 | EE | N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Measuring and modeling FPGA clock variability. FPGA 2008: 258 |
| 2 | EE | Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole: Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704 |
| 1 | EE | N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Characterisation of FPGA Clock Variability. ISVLSI 2008: 322-328 |
| 1 | Peter Y. K. Cheung | [1] [2] [3] |
| 2 | N. Pete Sedcole | [1] [2] [3] |